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Searched refs:HHI_GP0_PLL_CNTL2 (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h19 #define HHI_GP0_PLL_CNTL2 0x44 macro
H A Dclock-gx.h20 #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ macro
/openbmc/linux/drivers/clk/meson/
H A Daxg.h20 #define HHI_GP0_PLL_CNTL2 0x44 macro
H A Dgxbb.h21 #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ macro
H A Dg12a.h26 #define HHI_GP0_PLL_CNTL2 0x048 macro
H A Dgxbb.c432 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },
480 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
H A Daxg.c183 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
H A Dg12a.c1617 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 },