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Searched refs:HHI_GP0_PLL_CNTL1 (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h24 #define HHI_GP0_PLL_CNTL1 0x58 macro
H A Dclock-gx.h24 #define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */ macro
/openbmc/linux/drivers/clk/meson/
H A Daxg.h25 #define HHI_GP0_PLL_CNTL1 0x58 macro
H A Dgxbb.h25 #define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */ macro
H A Dg12a.h25 #define HHI_GP0_PLL_CNTL1 0x044 macro
H A Daxg.c182 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
207 .reg_off = HHI_GP0_PLL_CNTL1,
H A Dgxbb.c479 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
504 .reg_off = HHI_GP0_PLL_CNTL1,
H A Dg12a.c1616 { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 },
1642 .reg_off = HHI_GP0_PLL_CNTL1,