Searched refs:HHI_GP0_PLL_CNTL (Results 1 – 6 of 6) sorted by relevance
/openbmc/u-boot/arch/arm/include/asm/arch-meson/ |
H A D | clock-axg.h | 18 #define HHI_GP0_PLL_CNTL 0x40 macro
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H A D | clock-gx.h | 19 #define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ macro
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/openbmc/linux/drivers/clk/meson/ |
H A D | axg.h | 19 #define HHI_GP0_PLL_CNTL 0x40 macro
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H A D | gxbb.h | 20 #define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ macro
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H A D | gxbb.c | 440 .reg_off = HHI_GP0_PLL_CNTL, 445 .reg_off = HHI_GP0_PLL_CNTL, 450 .reg_off = HHI_GP0_PLL_CNTL, 455 .reg_off = HHI_GP0_PLL_CNTL, 460 .reg_off = HHI_GP0_PLL_CNTL, 489 .reg_off = HHI_GP0_PLL_CNTL, 494 .reg_off = HHI_GP0_PLL_CNTL, 499 .reg_off = HHI_GP0_PLL_CNTL, 509 .reg_off = HHI_GP0_PLL_CNTL, 514 .reg_off = HHI_GP0_PLL_CNTL, [all …]
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H A D | axg.c | 192 .reg_off = HHI_GP0_PLL_CNTL, 197 .reg_off = HHI_GP0_PLL_CNTL, 202 .reg_off = HHI_GP0_PLL_CNTL, 212 .reg_off = HHI_GP0_PLL_CNTL, 217 .reg_off = HHI_GP0_PLL_CNTL, 237 .offset = HHI_GP0_PLL_CNTL,
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