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Searched refs:HCLK (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dfsmc-nand.txt19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dst,nomadik.txt34 HCLK nodes: these represent the clock gates on individual
35 lines from the HCLK clock tree and the gate for individual
38 Requires properties for the HCLK nodes:
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmtk-sd.yaml191 - description: HCLK which used for host
211 - description: HCLK which used for host
244 - description: HCLK which used for host
269 - description: HCLK which used for host
289 - description: HCLK which used for host
H A Dsdhci-msm.yaml74 - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
/openbmc/u-boot/arch/arm/mach-imx/mx3/
H A DKconfig19 int "i.MX31 HCLK frequency"
/openbmc/linux/include/video/
H A Dkyro.h33 u32 HCLK; /* Hor Clock */ member
/openbmc/linux/include/dt-bindings/clock/
H A Dsamsung,s3c64xx-clock.h27 #define HCLK 8 macro
H A Dstm32h7-clks.h3 #define HCLK 1 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dstm32h7-clks.h3 #define HCLK 1 macro
/openbmc/linux/drivers/mmc/host/
H A Dtoshsd.h11 #define HCLK 33000000 /* 33 MHz (PCI clock) */ macro
H A Dtoshsd.c86 while (ios->clock < HCLK / div) in __toshsd_set_ios()
642 mmc->f_min = HCLK / 512; in toshsd_probe()
643 mmc->f_max = HCLK; in toshsd_probe()
/openbmc/linux/drivers/clk/samsung/
H A Dclk-s3c64xx.c163 DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
317 ALIAS(HCLK, NULL, "hclk"),
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Darm,pl11x.yaml65 - description: The HCLK AHB slave clock for the register access.
/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
232 /* The PCLK domain uses HCLK right off */
/openbmc/linux/drivers/video/fbdev/kyro/
H A Dfbdev.c509 par->HCLK = (1000000000 + (lineclock / 2)) / lineclock; in kyrofb_set_par()
/openbmc/linux/drivers/clk/nxp/
H A Dclk-lpc32xx.c213 LPC32XX_CLK_DEFINE(HCLK, "hclk", CLK_IGNORE_UNUSED,
1249 LPC32XX_DEFINE_GATE(HCLK, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
/openbmc/linux/drivers/clk/
H A Dclk-stm32h7.c517 hws[HCLK] = clk_hw_register_divider_table(NULL, "hclk", "d1cpre", in register_core_and_bus_clocks()