Searched refs:GPR (Results 1 – 9 of 9) sorted by relevance
| /openbmc/qemu/disas/ |
| H A D | nanomips.c | 405 static const char *GPR(uint64 reg, Dis_info *info) in GPR() function
435 reg_list[counter + 1] = (char *)GPR(this_rt, info); in save_restore_list()
1479 const char *rt = GPR(rt_value, info); in ABSQ_S_PH()
1480 const char *rs = GPR(rs_value, info); in ABSQ_S_PH()
1501 const char *rt = GPR(rt_value, info); in ABSQ_S_QB()
1502 const char *rs = GPR(rs_value, info); in ABSQ_S_QB()
1523 const char *rt = GPR(rt_value, info); in ABSQ_S_W()
1524 const char *rs = GPR(rs_value, info); in ABSQ_S_W()
1545 const char *rs = GPR(rs_value, info); in ACLR()
1567 const char *rd = GPR(rd_value, info); in ADD()
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| /openbmc/u-boot/arch/arm/cpu/arm920t/imx/ |
| H A D | generic.c | 39 GPR(port) |= (1<<pin); in imx_gpio_mode()
41 GPR(port) &= ~(1<<pin); in imx_gpio_mode()
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| /openbmc/u-boot/doc/ |
| H A D | README.NDS32 | 15 - 32 32-bit General Purpose Registers (GPR).
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| /openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/ |
| H A D | 0001-FF-A-v15-arm64-smccc-add-support-for-SMCCCv1.2-x0-x1.patch | 55 + /* Save `res` and free a GPR that won't be clobbered */
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| /openbmc/u-boot/arch/arm/include/asm/arch-imx/ |
| H A D | imx-regs.h | 125 #define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) macro
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| /openbmc/qemu/target/hexagon/ |
| H A D | README | 208 runtime information for each thread and contains stuff like the GPR and
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| /openbmc/qemu/target/hexagon/imported/ |
| H A D | compare.idef | 56 /* Compare and put result in GPR */
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| /openbmc/qemu/target/i386/tcg/ |
| H A D | decode-new.c.inc | 2020 case X86_TYPE_B: /* VEX.vvvv selects a GPR */
2056 case X86_TYPE_G: /* REG in the modrm byte selects a GPR */
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| /openbmc/qemu/tcg/riscv/ |
| H A D | tcg-target.c.inc | 674 * Vector registers uses the same 5 lower bits as GPR registers,
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