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Searched refs:GPLL0 (Results 1 – 25 of 95) sorted by relevance

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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,mmcc.yaml113 - description: MMSS GPLL0 voted clock
114 - description: GPLL0 voted clock
141 - description: MMSS GPLL0 voted clock
142 - description: GPLL0 voted clock
180 - description: MMSS GPLL0 voted clock
181 - description: GPLL0 clock
182 - description: GPLL0 voted clock
H A Dqcom,sm6115-gpucc.yaml26 - description: GPLL0 main branch source
27 - description: GPLL0 main div source
H A Dqcom,gpucc-sdm660.yaml27 - description: GPLL0 main gpu branch
28 - description: GPLL0 divider gpu branch
H A Dqcom,sm8450-gpucc.yaml30 - description: GPLL0 main branch source
31 - description: GPLL0 div branch source
H A Dqcom,sm6375-gpucc.yaml26 - description: GPLL0 main branch source
27 - description: GPLL0 div branch source
H A Dqcom,qcm2290-dispcc.yaml26 - description: GPLL0 source from GCC
27 - description: GPLL0 div source from GCC
H A Dqcom,sdm845-dispcc.yaml28 - description: GPLL0 source from GCC
29 - description: GPLL0 div source from GCC
H A Dqcom,gpucc.yaml44 - description: GPLL0 main branch source
45 - description: GPLL0 div branch source
H A Dqcom,sm6125-gpucc.yaml26 - description: GPLL0 main branch source
H A Dqcom,sm6375-dispcc.yaml28 - description: GPLL0 source from GCC
H A Dqcom,sm6115-dispcc.yaml29 - description: GPLL0 DISP DIV clock from GCC
H A Dqcom,msm8998-gpucc.yaml25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,osm-l3.yaml66 #define GPLL0 165
73 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
/openbmc/linux/include/dt-bindings/clock/
H A Dqcom,gcc-mdm9607.h9 #define GPLL0 0 macro
H A Dqcom,gcc-sdx55.h10 #define GPLL0 3 macro
H A Dqcom,gcc-sdx65.h10 #define GPLL0 0 macro
H A Dqcom,gcc-sc7180.h11 #define GPLL0 1 macro
H A Dqcom,gcc-sdm660.h111 #define GPLL0 101 macro
H A Dqcom,gcc-sm6350.h11 #define GPLL0 0 macro
H A Dqcom,gcc-msm8994.h11 #define GPLL0 1 macro
H A Dqcom,gcc-msm8916.h9 #define GPLL0 0 macro
H A Dqcom,sm7150-gcc.h13 #define GPLL0 1 macro
H A Dqcom,sdx75-gcc.h10 #define GPLL0 0 macro
H A Dqcom,gcc-msm8917.h149 #define GPLL0 142 macro
H A Dqcom,gcc-qcm2290.h10 #define GPLL0 0 macro

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