19c92ab61SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2b5f5f525SJoonwoo Park /*
3b5f5f525SJoonwoo Park  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
4b5f5f525SJoonwoo Park  */
5b5f5f525SJoonwoo Park 
6b5f5f525SJoonwoo Park #ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
7b5f5f525SJoonwoo Park #define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
8b5f5f525SJoonwoo Park 
9b5f5f525SJoonwoo Park #define BLSP1_QUP1_I2C_APPS_CLK_SRC				0
10b5f5f525SJoonwoo Park #define BLSP1_QUP1_SPI_APPS_CLK_SRC				1
11b5f5f525SJoonwoo Park #define BLSP1_QUP2_I2C_APPS_CLK_SRC				2
12b5f5f525SJoonwoo Park #define BLSP1_QUP2_SPI_APPS_CLK_SRC				3
13b5f5f525SJoonwoo Park #define BLSP1_QUP3_I2C_APPS_CLK_SRC				4
14b5f5f525SJoonwoo Park #define BLSP1_QUP3_SPI_APPS_CLK_SRC				5
15b5f5f525SJoonwoo Park #define BLSP1_QUP4_I2C_APPS_CLK_SRC				6
16b5f5f525SJoonwoo Park #define BLSP1_QUP4_SPI_APPS_CLK_SRC				7
17b5f5f525SJoonwoo Park #define BLSP1_QUP5_I2C_APPS_CLK_SRC				8
18b5f5f525SJoonwoo Park #define BLSP1_QUP5_SPI_APPS_CLK_SRC				9
19b5f5f525SJoonwoo Park #define BLSP1_QUP6_I2C_APPS_CLK_SRC				10
20b5f5f525SJoonwoo Park #define BLSP1_QUP6_SPI_APPS_CLK_SRC				11
21b5f5f525SJoonwoo Park #define BLSP1_UART1_APPS_CLK_SRC				12
22b5f5f525SJoonwoo Park #define BLSP1_UART2_APPS_CLK_SRC				13
23b5f5f525SJoonwoo Park #define BLSP1_UART3_APPS_CLK_SRC				14
24b5f5f525SJoonwoo Park #define BLSP2_QUP1_I2C_APPS_CLK_SRC				15
25b5f5f525SJoonwoo Park #define BLSP2_QUP1_SPI_APPS_CLK_SRC				16
26b5f5f525SJoonwoo Park #define BLSP2_QUP2_I2C_APPS_CLK_SRC				17
27b5f5f525SJoonwoo Park #define BLSP2_QUP2_SPI_APPS_CLK_SRC				18
28b5f5f525SJoonwoo Park #define BLSP2_QUP3_I2C_APPS_CLK_SRC				19
29b5f5f525SJoonwoo Park #define BLSP2_QUP3_SPI_APPS_CLK_SRC				20
30b5f5f525SJoonwoo Park #define BLSP2_QUP4_I2C_APPS_CLK_SRC				21
31b5f5f525SJoonwoo Park #define BLSP2_QUP4_SPI_APPS_CLK_SRC				22
32b5f5f525SJoonwoo Park #define BLSP2_QUP5_I2C_APPS_CLK_SRC				23
33b5f5f525SJoonwoo Park #define BLSP2_QUP5_SPI_APPS_CLK_SRC				24
34b5f5f525SJoonwoo Park #define BLSP2_QUP6_I2C_APPS_CLK_SRC				25
35b5f5f525SJoonwoo Park #define BLSP2_QUP6_SPI_APPS_CLK_SRC				26
36b5f5f525SJoonwoo Park #define BLSP2_UART1_APPS_CLK_SRC				27
37b5f5f525SJoonwoo Park #define BLSP2_UART2_APPS_CLK_SRC				28
38b5f5f525SJoonwoo Park #define BLSP2_UART3_APPS_CLK_SRC				29
39b5f5f525SJoonwoo Park #define GCC_AGGRE1_NOC_XO_CLK					30
40b5f5f525SJoonwoo Park #define GCC_AGGRE1_UFS_AXI_CLK					31
41b5f5f525SJoonwoo Park #define GCC_AGGRE1_USB3_AXI_CLK					32
42b5f5f525SJoonwoo Park #define GCC_APSS_QDSS_TSCTR_DIV2_CLK				33
43b5f5f525SJoonwoo Park #define GCC_APSS_QDSS_TSCTR_DIV8_CLK				34
44b5f5f525SJoonwoo Park #define GCC_BIMC_HMSS_AXI_CLK					35
45b5f5f525SJoonwoo Park #define GCC_BIMC_MSS_Q6_AXI_CLK					36
46b5f5f525SJoonwoo Park #define GCC_BLSP1_AHB_CLK					37
47b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP1_I2C_APPS_CLK				38
48b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP1_SPI_APPS_CLK				39
49b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP2_I2C_APPS_CLK				40
50b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP2_SPI_APPS_CLK				41
51b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP3_I2C_APPS_CLK				42
52b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP3_SPI_APPS_CLK				43
53b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP4_I2C_APPS_CLK				44
54b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP4_SPI_APPS_CLK				45
55b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP5_I2C_APPS_CLK				46
56b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP5_SPI_APPS_CLK				47
57b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP6_I2C_APPS_CLK				48
58b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP6_SPI_APPS_CLK				49
59b5f5f525SJoonwoo Park #define GCC_BLSP1_SLEEP_CLK					50
60b5f5f525SJoonwoo Park #define GCC_BLSP1_UART1_APPS_CLK				51
61b5f5f525SJoonwoo Park #define GCC_BLSP1_UART2_APPS_CLK				52
62b5f5f525SJoonwoo Park #define GCC_BLSP1_UART3_APPS_CLK				53
63b5f5f525SJoonwoo Park #define GCC_BLSP2_AHB_CLK					54
64b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP1_I2C_APPS_CLK				55
65b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP1_SPI_APPS_CLK				56
66b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP2_I2C_APPS_CLK				57
67b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP2_SPI_APPS_CLK				58
68b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP3_I2C_APPS_CLK				59
69b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP3_SPI_APPS_CLK				60
70b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP4_I2C_APPS_CLK				61
71b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP4_SPI_APPS_CLK				62
72b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP5_I2C_APPS_CLK				63
73b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP5_SPI_APPS_CLK				64
74b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP6_I2C_APPS_CLK				65
75b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP6_SPI_APPS_CLK				66
76b5f5f525SJoonwoo Park #define GCC_BLSP2_SLEEP_CLK					67
77b5f5f525SJoonwoo Park #define GCC_BLSP2_UART1_APPS_CLK				68
78b5f5f525SJoonwoo Park #define GCC_BLSP2_UART2_APPS_CLK				69
79b5f5f525SJoonwoo Park #define GCC_BLSP2_UART3_APPS_CLK				70
80b5f5f525SJoonwoo Park #define GCC_CFG_NOC_USB3_AXI_CLK				71
81b5f5f525SJoonwoo Park #define GCC_GP1_CLK						72
82b5f5f525SJoonwoo Park #define GCC_GP2_CLK						73
83b5f5f525SJoonwoo Park #define GCC_GP3_CLK						74
84b5f5f525SJoonwoo Park #define GCC_GPU_BIMC_GFX_CLK					75
85b5f5f525SJoonwoo Park #define GCC_GPU_BIMC_GFX_SRC_CLK				76
86b5f5f525SJoonwoo Park #define GCC_GPU_CFG_AHB_CLK					77
87b5f5f525SJoonwoo Park #define GCC_GPU_SNOC_DVM_GFX_CLK				78
88b5f5f525SJoonwoo Park #define GCC_HMSS_AHB_CLK					79
89b5f5f525SJoonwoo Park #define GCC_HMSS_AT_CLK						80
90b5f5f525SJoonwoo Park #define GCC_HMSS_DVM_BUS_CLK					81
91b5f5f525SJoonwoo Park #define GCC_HMSS_RBCPR_CLK					82
92b5f5f525SJoonwoo Park #define GCC_HMSS_TRIG_CLK					83
93b5f5f525SJoonwoo Park #define GCC_LPASS_AT_CLK					84
94b5f5f525SJoonwoo Park #define GCC_LPASS_TRIG_CLK					85
95b5f5f525SJoonwoo Park #define GCC_MMSS_NOC_CFG_AHB_CLK				86
96b5f5f525SJoonwoo Park #define GCC_MMSS_QM_AHB_CLK					87
97b5f5f525SJoonwoo Park #define GCC_MMSS_QM_CORE_CLK					88
98b5f5f525SJoonwoo Park #define GCC_MMSS_SYS_NOC_AXI_CLK				89
99b5f5f525SJoonwoo Park #define GCC_MSS_AT_CLK						90
100b5f5f525SJoonwoo Park #define GCC_PCIE_0_AUX_CLK					91
101b5f5f525SJoonwoo Park #define GCC_PCIE_0_CFG_AHB_CLK					92
102b5f5f525SJoonwoo Park #define GCC_PCIE_0_MSTR_AXI_CLK					93
103b5f5f525SJoonwoo Park #define GCC_PCIE_0_PIPE_CLK					94
104b5f5f525SJoonwoo Park #define GCC_PCIE_0_SLV_AXI_CLK					95
105b5f5f525SJoonwoo Park #define GCC_PCIE_PHY_AUX_CLK					96
106b5f5f525SJoonwoo Park #define GCC_PDM2_CLK						97
107b5f5f525SJoonwoo Park #define GCC_PDM_AHB_CLK						98
108b5f5f525SJoonwoo Park #define GCC_PDM_XO4_CLK						99
109b5f5f525SJoonwoo Park #define GCC_PRNG_AHB_CLK					100
110b5f5f525SJoonwoo Park #define GCC_SDCC2_AHB_CLK					101
111b5f5f525SJoonwoo Park #define GCC_SDCC2_APPS_CLK					102
112b5f5f525SJoonwoo Park #define GCC_SDCC4_AHB_CLK					103
113b5f5f525SJoonwoo Park #define GCC_SDCC4_APPS_CLK					104
114b5f5f525SJoonwoo Park #define GCC_TSIF_AHB_CLK					105
115b5f5f525SJoonwoo Park #define GCC_TSIF_INACTIVITY_TIMERS_CLK				106
116b5f5f525SJoonwoo Park #define GCC_TSIF_REF_CLK					107
117b5f5f525SJoonwoo Park #define GCC_UFS_AHB_CLK						108
118b5f5f525SJoonwoo Park #define GCC_UFS_AXI_CLK						109
119b5f5f525SJoonwoo Park #define GCC_UFS_ICE_CORE_CLK					110
120b5f5f525SJoonwoo Park #define GCC_UFS_PHY_AUX_CLK					111
121b5f5f525SJoonwoo Park #define GCC_UFS_RX_SYMBOL_0_CLK					112
122b5f5f525SJoonwoo Park #define GCC_UFS_RX_SYMBOL_1_CLK					113
123b5f5f525SJoonwoo Park #define GCC_UFS_TX_SYMBOL_0_CLK					114
124b5f5f525SJoonwoo Park #define GCC_UFS_UNIPRO_CORE_CLK					115
125b5f5f525SJoonwoo Park #define GCC_USB30_MASTER_CLK					116
126b5f5f525SJoonwoo Park #define GCC_USB30_MOCK_UTMI_CLK					117
127b5f5f525SJoonwoo Park #define GCC_USB30_SLEEP_CLK					118
128b5f5f525SJoonwoo Park #define GCC_USB3_PHY_AUX_CLK					119
129b5f5f525SJoonwoo Park #define GCC_USB3_PHY_PIPE_CLK					120
130b5f5f525SJoonwoo Park #define GCC_USB_PHY_CFG_AHB2PHY_CLK				121
131b5f5f525SJoonwoo Park #define GP1_CLK_SRC						122
132b5f5f525SJoonwoo Park #define GP2_CLK_SRC						123
133b5f5f525SJoonwoo Park #define GP3_CLK_SRC						124
134b5f5f525SJoonwoo Park #define GPLL0							125
135b5f5f525SJoonwoo Park #define GPLL0_OUT_EVEN						126
136b5f5f525SJoonwoo Park #define GPLL0_OUT_MAIN						127
137b5f5f525SJoonwoo Park #define GPLL0_OUT_ODD						128
138b5f5f525SJoonwoo Park #define GPLL0_OUT_TEST						129
139b5f5f525SJoonwoo Park #define GPLL1							130
140b5f5f525SJoonwoo Park #define GPLL1_OUT_EVEN						131
141b5f5f525SJoonwoo Park #define GPLL1_OUT_MAIN						132
142b5f5f525SJoonwoo Park #define GPLL1_OUT_ODD						133
143b5f5f525SJoonwoo Park #define GPLL1_OUT_TEST						134
144b5f5f525SJoonwoo Park #define GPLL2							135
145b5f5f525SJoonwoo Park #define GPLL2_OUT_EVEN						136
146b5f5f525SJoonwoo Park #define GPLL2_OUT_MAIN						137
147b5f5f525SJoonwoo Park #define GPLL2_OUT_ODD						138
148b5f5f525SJoonwoo Park #define GPLL2_OUT_TEST						139
149b5f5f525SJoonwoo Park #define GPLL3							140
150b5f5f525SJoonwoo Park #define GPLL3_OUT_EVEN						141
151b5f5f525SJoonwoo Park #define GPLL3_OUT_MAIN						142
152b5f5f525SJoonwoo Park #define GPLL3_OUT_ODD						143
153b5f5f525SJoonwoo Park #define GPLL3_OUT_TEST						144
154b5f5f525SJoonwoo Park #define GPLL4							145
155b5f5f525SJoonwoo Park #define GPLL4_OUT_EVEN						146
156b5f5f525SJoonwoo Park #define GPLL4_OUT_MAIN						147
157b5f5f525SJoonwoo Park #define GPLL4_OUT_ODD						148
158b5f5f525SJoonwoo Park #define GPLL4_OUT_TEST						149
159b5f5f525SJoonwoo Park #define GPLL6							150
160b5f5f525SJoonwoo Park #define GPLL6_OUT_EVEN						151
161b5f5f525SJoonwoo Park #define GPLL6_OUT_MAIN						152
162b5f5f525SJoonwoo Park #define GPLL6_OUT_ODD						153
163b5f5f525SJoonwoo Park #define GPLL6_OUT_TEST						154
164b5f5f525SJoonwoo Park #define HMSS_AHB_CLK_SRC					155
165b5f5f525SJoonwoo Park #define HMSS_RBCPR_CLK_SRC					156
166b5f5f525SJoonwoo Park #define PCIE_AUX_CLK_SRC					157
167b5f5f525SJoonwoo Park #define PDM2_CLK_SRC						158
168b5f5f525SJoonwoo Park #define SDCC2_APPS_CLK_SRC					159
169b5f5f525SJoonwoo Park #define SDCC4_APPS_CLK_SRC					160
170b5f5f525SJoonwoo Park #define TSIF_REF_CLK_SRC					161
171b5f5f525SJoonwoo Park #define UFS_AXI_CLK_SRC						162
172b5f5f525SJoonwoo Park #define USB30_MASTER_CLK_SRC					163
173b5f5f525SJoonwoo Park #define USB30_MOCK_UTMI_CLK_SRC					164
174b5f5f525SJoonwoo Park #define USB3_PHY_AUX_CLK_SRC					165
17530bc0b98SBjorn Andersson #define GCC_USB3_CLKREF_CLK					166
17630bc0b98SBjorn Andersson #define GCC_HDMI_CLKREF_CLK					167
17730bc0b98SBjorn Andersson #define GCC_UFS_CLKREF_CLK					168
17830bc0b98SBjorn Andersson #define GCC_PCIE_CLKREF_CLK					169
17930bc0b98SBjorn Andersson #define GCC_RX1_USB2_CLKREF_CLK					170
18095183d38SJeffrey Hugo #define GCC_MSS_CFG_AHB_CLK					171
18195183d38SJeffrey Hugo #define GCC_BOOT_ROM_AHB_CLK					172
18295183d38SJeffrey Hugo #define GCC_MSS_GPLL0_DIV_CLK_SRC				173
18395183d38SJeffrey Hugo #define GCC_MSS_SNOC_AXI_CLK					174
18495183d38SJeffrey Hugo #define GCC_MSS_MNOC_BIMC_AXI_CLK				175
185db2c7c0aSJeffrey Hugo #define GCC_BIMC_GFX_CLK					176
186b1e8d713SJeffrey Hugo #define UFS_UNIPRO_CORE_CLK_SRC					177
18768e5d392SAngeloGioacchino Del Regno #define GCC_MMSS_GPLL0_CLK					178
188e9f322f7SAngeloGioacchino Del Regno #define HMSS_GPLL0_CLK_SRC					179
189368cfcbaSMichael Srba #define GCC_IM_SLEEP						180
190368cfcbaSMichael Srba #define AGGRE2_SNOC_NORTH_AXI					181
191368cfcbaSMichael Srba #define SSC_XO							182
192368cfcbaSMichael Srba #define SSC_CNOC_AHBS_CLK					183
193*238e192bSKonrad Dybcio #define GCC_MMSS_GPLL0_DIV_CLK					184
194*238e192bSKonrad Dybcio #define GCC_GPU_GPLL0_DIV_CLK					185
195*238e192bSKonrad Dybcio #define GCC_GPU_GPLL0_CLK					186
196b5f5f525SJoonwoo Park 
197b5f5f525SJoonwoo Park #define PCIE_0_GDSC						0
198b5f5f525SJoonwoo Park #define UFS_GDSC						1
199b5f5f525SJoonwoo Park #define USB_30_GDSC						2
200b5f5f525SJoonwoo Park 
201b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP1_BCR					0
202b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP2_BCR					1
203b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP3_BCR					2
204b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP4_BCR					3
205b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP5_BCR					4
206b5f5f525SJoonwoo Park #define GCC_BLSP1_QUP6_BCR					5
207b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP1_BCR					6
208b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP2_BCR					7
209b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP3_BCR					8
210b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP4_BCR					9
211b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP5_BCR					10
212b5f5f525SJoonwoo Park #define GCC_BLSP2_QUP6_BCR					11
213b5f5f525SJoonwoo Park #define GCC_PCIE_0_BCR						12
214b5f5f525SJoonwoo Park #define GCC_PDM_BCR						13
215b5f5f525SJoonwoo Park #define GCC_SDCC2_BCR						14
216b5f5f525SJoonwoo Park #define GCC_SDCC4_BCR						15
217b5f5f525SJoonwoo Park #define GCC_TSIF_BCR						16
218b5f5f525SJoonwoo Park #define GCC_UFS_BCR						17
219b5f5f525SJoonwoo Park #define GCC_USB_30_BCR						18
220c0cb7c7eSJeffrey Hugo #define GCC_SYSTEM_NOC_BCR					19
221c0cb7c7eSJeffrey Hugo #define GCC_CONFIG_NOC_BCR					20
222c0cb7c7eSJeffrey Hugo #define GCC_AHB2PHY_EAST_BCR					21
223c0cb7c7eSJeffrey Hugo #define GCC_IMEM_BCR						22
224c0cb7c7eSJeffrey Hugo #define GCC_PIMEM_BCR						23
225c0cb7c7eSJeffrey Hugo #define GCC_MMSS_BCR						24
226c0cb7c7eSJeffrey Hugo #define GCC_QDSS_BCR						25
227c0cb7c7eSJeffrey Hugo #define GCC_WCSS_BCR						26
228c0cb7c7eSJeffrey Hugo #define GCC_BLSP1_BCR						27
229c0cb7c7eSJeffrey Hugo #define GCC_BLSP1_UART1_BCR					28
230c0cb7c7eSJeffrey Hugo #define GCC_BLSP1_UART2_BCR					29
231c0cb7c7eSJeffrey Hugo #define GCC_BLSP1_UART3_BCR					30
232c0cb7c7eSJeffrey Hugo #define GCC_CM_PHY_REFGEN1_BCR					31
233c0cb7c7eSJeffrey Hugo #define GCC_CM_PHY_REFGEN2_BCR					32
234c0cb7c7eSJeffrey Hugo #define GCC_BLSP2_BCR						33
235c0cb7c7eSJeffrey Hugo #define GCC_BLSP2_UART1_BCR					34
236c0cb7c7eSJeffrey Hugo #define GCC_BLSP2_UART2_BCR					35
237c0cb7c7eSJeffrey Hugo #define GCC_BLSP2_UART3_BCR					36
238c0cb7c7eSJeffrey Hugo #define GCC_SRAM_SENSOR_BCR					37
239c0cb7c7eSJeffrey Hugo #define GCC_PRNG_BCR						38
240c0cb7c7eSJeffrey Hugo #define GCC_TSIF_0_RESET					39
241c0cb7c7eSJeffrey Hugo #define GCC_TSIF_1_RESET					40
242c0cb7c7eSJeffrey Hugo #define GCC_TCSR_BCR						41
243c0cb7c7eSJeffrey Hugo #define GCC_BOOT_ROM_BCR					42
244c0cb7c7eSJeffrey Hugo #define GCC_MSG_RAM_BCR						43
245c0cb7c7eSJeffrey Hugo #define GCC_TLMM_BCR						44
246c0cb7c7eSJeffrey Hugo #define GCC_MPM_BCR						45
247c0cb7c7eSJeffrey Hugo #define GCC_SEC_CTRL_BCR					46
248c0cb7c7eSJeffrey Hugo #define GCC_SPMI_BCR						47
249c0cb7c7eSJeffrey Hugo #define GCC_SPDM_BCR						48
250c0cb7c7eSJeffrey Hugo #define GCC_CE1_BCR						49
251c0cb7c7eSJeffrey Hugo #define GCC_BIMC_BCR						50
252c0cb7c7eSJeffrey Hugo #define GCC_SNOC_BUS_TIMEOUT0_BCR				51
253c0cb7c7eSJeffrey Hugo #define GCC_SNOC_BUS_TIMEOUT1_BCR				52
254c0cb7c7eSJeffrey Hugo #define GCC_SNOC_BUS_TIMEOUT3_BCR				53
255c0cb7c7eSJeffrey Hugo #define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR				54
256c0cb7c7eSJeffrey Hugo #define GCC_PNOC_BUS_TIMEOUT0_BCR				55
257c0cb7c7eSJeffrey Hugo #define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR			56
258c0cb7c7eSJeffrey Hugo #define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR			57
259c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT0_BCR				58
260c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT1_BCR				59
261c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT2_BCR				60
262c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT3_BCR				61
263c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT4_BCR				62
264c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT5_BCR				63
265c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT6_BCR				64
266c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT7_BCR				65
267c0cb7c7eSJeffrey Hugo #define GCC_APB2JTAG_BCR					66
268c0cb7c7eSJeffrey Hugo #define GCC_RBCPR_CX_BCR					67
269c0cb7c7eSJeffrey Hugo #define GCC_RBCPR_MX_BCR					68
270c0cb7c7eSJeffrey Hugo #define GCC_USB3_PHY_BCR					69
271c0cb7c7eSJeffrey Hugo #define GCC_USB3PHY_PHY_BCR					70
272c0cb7c7eSJeffrey Hugo #define GCC_USB3_DP_PHY_BCR					71
273c0cb7c7eSJeffrey Hugo #define GCC_SSC_BCR						72
274c0cb7c7eSJeffrey Hugo #define GCC_SSC_RESET						73
275c0cb7c7eSJeffrey Hugo #define GCC_USB_PHY_CFG_AHB2PHY_BCR				74
276c0cb7c7eSJeffrey Hugo #define GCC_PCIE_0_LINK_DOWN_BCR				75
277c0cb7c7eSJeffrey Hugo #define GCC_PCIE_0_PHY_BCR					76
278c0cb7c7eSJeffrey Hugo #define GCC_PCIE_0_NOCSR_COM_PHY_BCR				77
279c0cb7c7eSJeffrey Hugo #define GCC_PCIE_PHY_BCR					78
280c0cb7c7eSJeffrey Hugo #define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR				79
281c0cb7c7eSJeffrey Hugo #define GCC_PCIE_PHY_CFG_AHB_BCR				80
282c0cb7c7eSJeffrey Hugo #define GCC_PCIE_PHY_COM_BCR					81
283c0cb7c7eSJeffrey Hugo #define GCC_GPU_BCR						82
284c0cb7c7eSJeffrey Hugo #define GCC_SPSS_BCR						83
285c0cb7c7eSJeffrey Hugo #define GCC_OBT_ODT_BCR						84
286c0cb7c7eSJeffrey Hugo #define GCC_VS_BCR						85
287c0cb7c7eSJeffrey Hugo #define GCC_MSS_VS_RESET					86
288c0cb7c7eSJeffrey Hugo #define GCC_GPU_VS_RESET					87
289c0cb7c7eSJeffrey Hugo #define GCC_APC0_VS_RESET					88
290c0cb7c7eSJeffrey Hugo #define GCC_APC1_VS_RESET					89
291c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT8_BCR				90
292c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT9_BCR				91
293c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT10_BCR				92
294c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT11_BCR				93
295c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT12_BCR				94
296c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT13_BCR				95
297c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT14_BCR				96
298c0cb7c7eSJeffrey Hugo #define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR				97
299c0cb7c7eSJeffrey Hugo #define GCC_AGGRE1_NOC_BCR					98
300c0cb7c7eSJeffrey Hugo #define GCC_AGGRE2_NOC_BCR					99
301c0cb7c7eSJeffrey Hugo #define GCC_DCC_BCR						100
302c0cb7c7eSJeffrey Hugo #define GCC_QREFS_VBG_CAL_BCR					101
303c0cb7c7eSJeffrey Hugo #define GCC_IPA_BCR						102
304c0cb7c7eSJeffrey Hugo #define GCC_GLM_BCR						103
305c0cb7c7eSJeffrey Hugo #define GCC_SKL_BCR						104
306c0cb7c7eSJeffrey Hugo #define GCC_MSMPU_BCR						105
307a1697abaSJeffrey Hugo #define GCC_QUSB2PHY_PRIM_BCR					106
308a1697abaSJeffrey Hugo #define GCC_QUSB2PHY_SEC_BCR					107
30995183d38SJeffrey Hugo #define GCC_MSS_RESTART						108
310b5f5f525SJoonwoo Park 
311b5f5f525SJoonwoo Park #endif
312