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Searched refs:GICV3_NS (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/hw/intc/
H A Darm_gicv3_kvm.c368 reg = c->gicr_statusr[GICV3_NS]; in kvm_arm_gicv3_put()
409 reg = s->gicd_statusr[GICV3_NS]; in kvm_arm_gicv3_put()
463 &c->icc_ctlr_el1[GICV3_NS], true); in kvm_arm_gicv3_put()
472 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & in kvm_arm_gicv3_put()
534 c->gicr_statusr[GICV3_NS] = reg; in kvm_arm_gicv3_get()
578 s->gicd_statusr[GICV3_NS] = reg; in kvm_arm_gicv3_get()
621 &c->icc_ctlr_el1[GICV3_NS], false); in kvm_arm_gicv3_get()
629 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & in kvm_arm_gicv3_get()
701 &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); in arm_gicv3_icc_reset()
703 c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; in arm_gicv3_icc_reset()
H A Darm_gicv3_cpuif.c970 cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { in icc_gprio_mask()
1392 return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1768 (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { in icc_bpr_read()
1813 (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { in icc_bpr_write()
2169 int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S; in icc_ctlr_el1_read()
2185 int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S; in icc_ctlr_el1_write()
2219 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
2222 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR) { in icc_ctlr_el3_read()
2225 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
2228 if (cs->icc_ctlr_el1[GICV3_NS] in icc_ctlr_el3_read()
[all...]
H A Darm_gicv3_common.c513 cs->gicr_statusr[GICV3_NS] = 0; in arm_gicv3_common_reset_hold()
558 s->gicd_statusr[GICV3_NS] = 0; in arm_gicv3_common_reset_hold()
/openbmc/qemu/include/hw/intc/
H A Darm_gicv3_common.h117 #define GICV3_NS 1 macro