Searched refs:FREQCR (Results 1 – 6 of 6) sorted by relevance
27 pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; in master_clk_init()36 int idx = (__raw_readw(FREQCR) & 0x0007); in module_clk_recalc()46 int idx = (__raw_readw(FREQCR) & 0x0007); in bus_clk_recalc()56 int idx = ((__raw_readw(FREQCR) >> 4) & 0x0007); in cpu_clk_recalc()
26 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; in master_clk_init()35 int idx = (__raw_readw(FREQCR) & 0x0007); in module_clk_recalc()45 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; in bus_clk_recalc()54 int idx = (__raw_readw(FREQCR) & 0x0007); in cpu_clk_recalc()
29 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult; in master_clk_init()38 int idx = (__raw_readw(FREQCR) & 0x0007); in module_clk_recalc()48 int idx = (__raw_readw(FREQCR) & 0x0007); in bus_clk_recalc()
25 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; in master_clk_init()34 int idx = (__raw_readw(FREQCR) & 0x0007); in module_clk_recalc()44 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; in bus_clk_recalc()
10 #define FREQCR 0xfffe0010 macro
11 #define FREQCR 0xf815ff80 macro