Searched refs:EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ (Results 1 – 1 of 1) sorted by relevance
55 #define EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ (0x0 << 0) macro115 *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ; in exynos4210_rate_to_clk()