1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
20b56e9a7SVivek Gautam /*
30b56e9a7SVivek Gautam * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4210 support
40b56e9a7SVivek Gautam *
50b56e9a7SVivek Gautam * Copyright (C) 2013 Samsung Electronics Co., Ltd.
60b56e9a7SVivek Gautam * Author: Kamil Debski <k.debski@samsung.com>
70b56e9a7SVivek Gautam */
80b56e9a7SVivek Gautam
90b56e9a7SVivek Gautam #include <linux/delay.h>
100b56e9a7SVivek Gautam #include <linux/io.h>
110b56e9a7SVivek Gautam #include <linux/phy/phy.h>
120b56e9a7SVivek Gautam #include <linux/regmap.h>
130b56e9a7SVivek Gautam #include "phy-samsung-usb2.h"
140b56e9a7SVivek Gautam
150b56e9a7SVivek Gautam /* Exynos USB PHY registers */
160b56e9a7SVivek Gautam
170b56e9a7SVivek Gautam /* PHY power control */
180b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR 0x0
190b56e9a7SVivek Gautam
200b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_PHY0_SUSPEND BIT(0)
210b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_PHY0_PWR BIT(3)
220b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR BIT(4)
230b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_PHY0_SLEEP BIT(5)
240b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_PHY0 ( \
250b56e9a7SVivek Gautam EXYNOS_4210_UPHYPWR_PHY0_SUSPEND | \
260b56e9a7SVivek Gautam EXYNOS_4210_UPHYPWR_PHY0_PWR | \
270b56e9a7SVivek Gautam EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR | \
280b56e9a7SVivek Gautam EXYNOS_4210_UPHYPWR_PHY0_SLEEP)
290b56e9a7SVivek Gautam
300b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_PHY1_SUSPEND BIT(6)
310b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_PHY1_PWR BIT(7)
320b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_PHY1_SLEEP BIT(8)
330b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_PHY1 ( \
340b56e9a7SVivek Gautam EXYNOS_4210_UPHYPWR_PHY1_SUSPEND | \
350b56e9a7SVivek Gautam EXYNOS_4210_UPHYPWR_PHY1_PWR | \
360b56e9a7SVivek Gautam EXYNOS_4210_UPHYPWR_PHY1_SLEEP)
370b56e9a7SVivek Gautam
380b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_HSIC0_SUSPEND BIT(9)
390b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_HSIC0_SLEEP BIT(10)
400b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_HSIC0 ( \
410b56e9a7SVivek Gautam EXYNOS_4210_UPHYPWR_HSIC0_SUSPEND | \
420b56e9a7SVivek Gautam EXYNOS_4210_UPHYPWR_HSIC0_SLEEP)
430b56e9a7SVivek Gautam
440b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_HSIC1_SUSPEND BIT(11)
450b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_HSIC1_SLEEP BIT(12)
460b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYPWR_HSIC1 ( \
470b56e9a7SVivek Gautam EXYNOS_4210_UPHYPWR_HSIC1_SUSPEND | \
480b56e9a7SVivek Gautam EXYNOS_4210_UPHYPWR_HSIC1_SLEEP)
490b56e9a7SVivek Gautam
500b56e9a7SVivek Gautam /* PHY clock control */
510b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYCLK 0x4
520b56e9a7SVivek Gautam
530b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYCLK_PHYFSEL_MASK (0x3 << 0)
540b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET 0
550b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ (0x0 << 0)
560b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ (0x3 << 0)
570b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
580b56e9a7SVivek Gautam
590b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYCLK_PHY0_ID_PULLUP BIT(2)
600b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYCLK_PHY0_COMMON_ON BIT(4)
610b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYCLK_PHY1_COMMON_ON BIT(7)
620b56e9a7SVivek Gautam
630b56e9a7SVivek Gautam /* PHY reset control */
640b56e9a7SVivek Gautam #define EXYNOS_4210_UPHYRST 0x8
650b56e9a7SVivek Gautam
660b56e9a7SVivek Gautam #define EXYNOS_4210_URSTCON_PHY0 BIT(0)
670b56e9a7SVivek Gautam #define EXYNOS_4210_URSTCON_OTG_HLINK BIT(1)
680b56e9a7SVivek Gautam #define EXYNOS_4210_URSTCON_OTG_PHYLINK BIT(2)
690b56e9a7SVivek Gautam #define EXYNOS_4210_URSTCON_PHY1_ALL BIT(3)
700b56e9a7SVivek Gautam #define EXYNOS_4210_URSTCON_PHY1_P0 BIT(4)
710b56e9a7SVivek Gautam #define EXYNOS_4210_URSTCON_PHY1_P1P2 BIT(5)
720b56e9a7SVivek Gautam #define EXYNOS_4210_URSTCON_HOST_LINK_ALL BIT(6)
730b56e9a7SVivek Gautam #define EXYNOS_4210_URSTCON_HOST_LINK_P0 BIT(7)
740b56e9a7SVivek Gautam #define EXYNOS_4210_URSTCON_HOST_LINK_P1 BIT(8)
750b56e9a7SVivek Gautam #define EXYNOS_4210_URSTCON_HOST_LINK_P2 BIT(9)
760b56e9a7SVivek Gautam
770b56e9a7SVivek Gautam /* Isolation, configured in the power management unit */
780b56e9a7SVivek Gautam #define EXYNOS_4210_USB_ISOL_DEVICE_OFFSET 0x704
790b56e9a7SVivek Gautam #define EXYNOS_4210_USB_ISOL_DEVICE BIT(0)
800b56e9a7SVivek Gautam #define EXYNOS_4210_USB_ISOL_HOST_OFFSET 0x708
810b56e9a7SVivek Gautam #define EXYNOS_4210_USB_ISOL_HOST BIT(0)
820b56e9a7SVivek Gautam
830b56e9a7SVivek Gautam /* USBYPHY1 Floating prevention */
840b56e9a7SVivek Gautam #define EXYNOS_4210_UPHY1CON 0x34
850b56e9a7SVivek Gautam #define EXYNOS_4210_UPHY1CON_FLOAT_PREVENTION 0x1
860b56e9a7SVivek Gautam
870b56e9a7SVivek Gautam /* Mode switching SUB Device <-> Host */
880b56e9a7SVivek Gautam #define EXYNOS_4210_MODE_SWITCH_OFFSET 0x21c
890b56e9a7SVivek Gautam #define EXYNOS_4210_MODE_SWITCH_MASK 1
900b56e9a7SVivek Gautam #define EXYNOS_4210_MODE_SWITCH_DEVICE 0
910b56e9a7SVivek Gautam #define EXYNOS_4210_MODE_SWITCH_HOST 1
920b56e9a7SVivek Gautam
930b56e9a7SVivek Gautam enum exynos4210_phy_id {
940b56e9a7SVivek Gautam EXYNOS4210_DEVICE,
950b56e9a7SVivek Gautam EXYNOS4210_HOST,
960b56e9a7SVivek Gautam EXYNOS4210_HSIC0,
970b56e9a7SVivek Gautam EXYNOS4210_HSIC1,
980b56e9a7SVivek Gautam EXYNOS4210_NUM_PHYS,
990b56e9a7SVivek Gautam };
1000b56e9a7SVivek Gautam
1010b56e9a7SVivek Gautam /*
1020b56e9a7SVivek Gautam * exynos4210_rate_to_clk() converts the supplied clock rate to the value that
1030b56e9a7SVivek Gautam * can be written to the phy register.
1040b56e9a7SVivek Gautam */
exynos4210_rate_to_clk(unsigned long rate,u32 * reg)1050b56e9a7SVivek Gautam static int exynos4210_rate_to_clk(unsigned long rate, u32 *reg)
1060b56e9a7SVivek Gautam {
1070b56e9a7SVivek Gautam switch (rate) {
1080b56e9a7SVivek Gautam case 12 * MHZ:
1090b56e9a7SVivek Gautam *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ;
1100b56e9a7SVivek Gautam break;
1110b56e9a7SVivek Gautam case 24 * MHZ:
1120b56e9a7SVivek Gautam *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ;
1130b56e9a7SVivek Gautam break;
1140b56e9a7SVivek Gautam case 48 * MHZ:
1150b56e9a7SVivek Gautam *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ;
1160b56e9a7SVivek Gautam break;
1170b56e9a7SVivek Gautam default:
1180b56e9a7SVivek Gautam return -EINVAL;
1190b56e9a7SVivek Gautam }
1200b56e9a7SVivek Gautam
1210b56e9a7SVivek Gautam return 0;
1220b56e9a7SVivek Gautam }
1230b56e9a7SVivek Gautam
exynos4210_isol(struct samsung_usb2_phy_instance * inst,bool on)1240b56e9a7SVivek Gautam static void exynos4210_isol(struct samsung_usb2_phy_instance *inst, bool on)
1250b56e9a7SVivek Gautam {
1260b56e9a7SVivek Gautam struct samsung_usb2_phy_driver *drv = inst->drv;
1270b56e9a7SVivek Gautam u32 offset;
1280b56e9a7SVivek Gautam u32 mask;
1290b56e9a7SVivek Gautam
1300b56e9a7SVivek Gautam switch (inst->cfg->id) {
1310b56e9a7SVivek Gautam case EXYNOS4210_DEVICE:
1320b56e9a7SVivek Gautam offset = EXYNOS_4210_USB_ISOL_DEVICE_OFFSET;
1330b56e9a7SVivek Gautam mask = EXYNOS_4210_USB_ISOL_DEVICE;
1340b56e9a7SVivek Gautam break;
1350b56e9a7SVivek Gautam case EXYNOS4210_HOST:
1360b56e9a7SVivek Gautam offset = EXYNOS_4210_USB_ISOL_HOST_OFFSET;
1370b56e9a7SVivek Gautam mask = EXYNOS_4210_USB_ISOL_HOST;
1380b56e9a7SVivek Gautam break;
1390b56e9a7SVivek Gautam default:
1400b56e9a7SVivek Gautam return;
1410b56e9a7SVivek Gautam }
1420b56e9a7SVivek Gautam
1430b56e9a7SVivek Gautam regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
1440b56e9a7SVivek Gautam }
1450b56e9a7SVivek Gautam
exynos4210_phy_pwr(struct samsung_usb2_phy_instance * inst,bool on)1460b56e9a7SVivek Gautam static void exynos4210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
1470b56e9a7SVivek Gautam {
1480b56e9a7SVivek Gautam struct samsung_usb2_phy_driver *drv = inst->drv;
1490b56e9a7SVivek Gautam u32 rstbits = 0;
1500b56e9a7SVivek Gautam u32 phypwr = 0;
1510b56e9a7SVivek Gautam u32 rst;
1520b56e9a7SVivek Gautam u32 pwr;
1530b56e9a7SVivek Gautam u32 clk;
1540b56e9a7SVivek Gautam
1550b56e9a7SVivek Gautam switch (inst->cfg->id) {
1560b56e9a7SVivek Gautam case EXYNOS4210_DEVICE:
1570b56e9a7SVivek Gautam phypwr = EXYNOS_4210_UPHYPWR_PHY0;
1580b56e9a7SVivek Gautam rstbits = EXYNOS_4210_URSTCON_PHY0;
1590b56e9a7SVivek Gautam break;
1600b56e9a7SVivek Gautam case EXYNOS4210_HOST:
1610b56e9a7SVivek Gautam phypwr = EXYNOS_4210_UPHYPWR_PHY1;
1620b56e9a7SVivek Gautam rstbits = EXYNOS_4210_URSTCON_PHY1_ALL |
1630b56e9a7SVivek Gautam EXYNOS_4210_URSTCON_PHY1_P0 |
1640b56e9a7SVivek Gautam EXYNOS_4210_URSTCON_PHY1_P1P2 |
1650b56e9a7SVivek Gautam EXYNOS_4210_URSTCON_HOST_LINK_ALL |
1660b56e9a7SVivek Gautam EXYNOS_4210_URSTCON_HOST_LINK_P0;
1670b56e9a7SVivek Gautam writel(on, drv->reg_phy + EXYNOS_4210_UPHY1CON);
1680b56e9a7SVivek Gautam break;
1690b56e9a7SVivek Gautam case EXYNOS4210_HSIC0:
1700b56e9a7SVivek Gautam phypwr = EXYNOS_4210_UPHYPWR_HSIC0;
1710b56e9a7SVivek Gautam rstbits = EXYNOS_4210_URSTCON_PHY1_P1P2 |
1720b56e9a7SVivek Gautam EXYNOS_4210_URSTCON_HOST_LINK_P1;
1730b56e9a7SVivek Gautam break;
1740b56e9a7SVivek Gautam case EXYNOS4210_HSIC1:
1750b56e9a7SVivek Gautam phypwr = EXYNOS_4210_UPHYPWR_HSIC1;
1760b56e9a7SVivek Gautam rstbits = EXYNOS_4210_URSTCON_PHY1_P1P2 |
1770b56e9a7SVivek Gautam EXYNOS_4210_URSTCON_HOST_LINK_P2;
1780b56e9a7SVivek Gautam break;
1790b56e9a7SVivek Gautam }
1800b56e9a7SVivek Gautam
1810b56e9a7SVivek Gautam if (on) {
1820b56e9a7SVivek Gautam clk = readl(drv->reg_phy + EXYNOS_4210_UPHYCLK);
1830b56e9a7SVivek Gautam clk &= ~EXYNOS_4210_UPHYCLK_PHYFSEL_MASK;
1840b56e9a7SVivek Gautam clk |= drv->ref_reg_val << EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET;
1850b56e9a7SVivek Gautam writel(clk, drv->reg_phy + EXYNOS_4210_UPHYCLK);
1860b56e9a7SVivek Gautam
1870b56e9a7SVivek Gautam pwr = readl(drv->reg_phy + EXYNOS_4210_UPHYPWR);
1880b56e9a7SVivek Gautam pwr &= ~phypwr;
1890b56e9a7SVivek Gautam writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR);
1900b56e9a7SVivek Gautam
1910b56e9a7SVivek Gautam rst = readl(drv->reg_phy + EXYNOS_4210_UPHYRST);
1920b56e9a7SVivek Gautam rst |= rstbits;
1930b56e9a7SVivek Gautam writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST);
1940b56e9a7SVivek Gautam udelay(10);
1950b56e9a7SVivek Gautam rst &= ~rstbits;
1960b56e9a7SVivek Gautam writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST);
1970b56e9a7SVivek Gautam /* The following delay is necessary for the reset sequence to be
1980b56e9a7SVivek Gautam * completed */
1990b56e9a7SVivek Gautam udelay(80);
2000b56e9a7SVivek Gautam } else {
2010b56e9a7SVivek Gautam pwr = readl(drv->reg_phy + EXYNOS_4210_UPHYPWR);
2020b56e9a7SVivek Gautam pwr |= phypwr;
2030b56e9a7SVivek Gautam writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR);
2040b56e9a7SVivek Gautam }
2050b56e9a7SVivek Gautam }
2060b56e9a7SVivek Gautam
exynos4210_power_on(struct samsung_usb2_phy_instance * inst)2070b56e9a7SVivek Gautam static int exynos4210_power_on(struct samsung_usb2_phy_instance *inst)
2080b56e9a7SVivek Gautam {
2090b56e9a7SVivek Gautam /* Order of initialisation is important - first power then isolation */
2100b56e9a7SVivek Gautam exynos4210_phy_pwr(inst, 1);
2110b56e9a7SVivek Gautam exynos4210_isol(inst, 0);
2120b56e9a7SVivek Gautam
2130b56e9a7SVivek Gautam return 0;
2140b56e9a7SVivek Gautam }
2150b56e9a7SVivek Gautam
exynos4210_power_off(struct samsung_usb2_phy_instance * inst)2160b56e9a7SVivek Gautam static int exynos4210_power_off(struct samsung_usb2_phy_instance *inst)
2170b56e9a7SVivek Gautam {
2180b56e9a7SVivek Gautam exynos4210_isol(inst, 1);
2190b56e9a7SVivek Gautam exynos4210_phy_pwr(inst, 0);
2200b56e9a7SVivek Gautam
2210b56e9a7SVivek Gautam return 0;
2220b56e9a7SVivek Gautam }
2230b56e9a7SVivek Gautam
2240b56e9a7SVivek Gautam
2250b56e9a7SVivek Gautam static const struct samsung_usb2_common_phy exynos4210_phys[] = {
2260b56e9a7SVivek Gautam {
2270b56e9a7SVivek Gautam .label = "device",
2280b56e9a7SVivek Gautam .id = EXYNOS4210_DEVICE,
2290b56e9a7SVivek Gautam .power_on = exynos4210_power_on,
2300b56e9a7SVivek Gautam .power_off = exynos4210_power_off,
2310b56e9a7SVivek Gautam },
2320b56e9a7SVivek Gautam {
2330b56e9a7SVivek Gautam .label = "host",
2340b56e9a7SVivek Gautam .id = EXYNOS4210_HOST,
2350b56e9a7SVivek Gautam .power_on = exynos4210_power_on,
2360b56e9a7SVivek Gautam .power_off = exynos4210_power_off,
2370b56e9a7SVivek Gautam },
2380b56e9a7SVivek Gautam {
2390b56e9a7SVivek Gautam .label = "hsic0",
2400b56e9a7SVivek Gautam .id = EXYNOS4210_HSIC0,
2410b56e9a7SVivek Gautam .power_on = exynos4210_power_on,
2420b56e9a7SVivek Gautam .power_off = exynos4210_power_off,
2430b56e9a7SVivek Gautam },
2440b56e9a7SVivek Gautam {
2450b56e9a7SVivek Gautam .label = "hsic1",
2460b56e9a7SVivek Gautam .id = EXYNOS4210_HSIC1,
2470b56e9a7SVivek Gautam .power_on = exynos4210_power_on,
2480b56e9a7SVivek Gautam .power_off = exynos4210_power_off,
2490b56e9a7SVivek Gautam },
2500b56e9a7SVivek Gautam };
2510b56e9a7SVivek Gautam
2520b56e9a7SVivek Gautam const struct samsung_usb2_phy_config exynos4210_usb2_phy_config = {
2530b56e9a7SVivek Gautam .has_mode_switch = 0,
2540b56e9a7SVivek Gautam .num_phys = EXYNOS4210_NUM_PHYS,
2550b56e9a7SVivek Gautam .phys = exynos4210_phys,
2560b56e9a7SVivek Gautam .rate_to_clk = exynos4210_rate_to_clk,
2570b56e9a7SVivek Gautam };
258