Searched refs:EPIMCR0 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | fsl_epu.c | 114 {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
115 {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
116 {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
117 {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
120 {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
121 {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
122 {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
123 {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
124 {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
125 {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
[all …]
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| H A D | fsl_epu.h | 29 #define EPIMCR0 0x100 macro
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