xref: /openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/fsl_epu.h (revision e8f80a5a)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2306fa012Schenhui zhao /*
3306fa012Schenhui zhao  * Copyright 2014 Freescale Semiconductor, Inc.
4306fa012Schenhui zhao  */
5306fa012Schenhui zhao 
6306fa012Schenhui zhao #ifndef __FSL_EPU_H
7306fa012Schenhui zhao #define __FSL_EPU_H
8306fa012Schenhui zhao 
9306fa012Schenhui zhao #include <asm/types.h>
10306fa012Schenhui zhao 
11306fa012Schenhui zhao #define FSL_STRIDE_4B	4
12306fa012Schenhui zhao #define FSL_STRIDE_8B	8
13306fa012Schenhui zhao 
14306fa012Schenhui zhao /* Block offsets */
15306fa012Schenhui zhao #define EPU_BLOCK_OFFSET	0x00000000
16306fa012Schenhui zhao 
17306fa012Schenhui zhao /* EPGCR (Event Processor Global Control Register) */
18306fa012Schenhui zhao #define EPGCR		0x000
19306fa012Schenhui zhao 
20306fa012Schenhui zhao /* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
21306fa012Schenhui zhao #define EPEVTCR0	0x050
22306fa012Schenhui zhao #define EPEVTCR9	0x074
23306fa012Schenhui zhao #define EPEVTCR_STRIDE	FSL_STRIDE_4B
24306fa012Schenhui zhao 
25306fa012Schenhui zhao /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
26306fa012Schenhui zhao #define EPXTRIGCR	0x090
27306fa012Schenhui zhao 
28306fa012Schenhui zhao /* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
29306fa012Schenhui zhao #define EPIMCR0		0x100
30306fa012Schenhui zhao #define EPIMCR31	0x17C
31306fa012Schenhui zhao #define EPIMCR_STRIDE	FSL_STRIDE_4B
32306fa012Schenhui zhao 
33306fa012Schenhui zhao /* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
34306fa012Schenhui zhao #define EPSMCR0		0x200
35306fa012Schenhui zhao #define EPSMCR15	0x278
36306fa012Schenhui zhao #define EPSMCR_STRIDE	FSL_STRIDE_8B
37306fa012Schenhui zhao 
38306fa012Schenhui zhao /* EPECR0-15 (Event Processor Event Control Registers) */
39306fa012Schenhui zhao #define EPECR0		0x300
40306fa012Schenhui zhao #define EPECR15		0x33C
41306fa012Schenhui zhao #define EPECR_STRIDE	FSL_STRIDE_4B
42306fa012Schenhui zhao 
43306fa012Schenhui zhao /* EPACR0-15 (Event Processor Action Control Registers) */
44306fa012Schenhui zhao #define EPACR0		0x400
45306fa012Schenhui zhao #define EPACR15		0x43C
46306fa012Schenhui zhao #define EPACR_STRIDE	FSL_STRIDE_4B
47306fa012Schenhui zhao 
48306fa012Schenhui zhao /* EPCCRi0-15 (Event Processor Counter Control Registers) */
49306fa012Schenhui zhao #define EPCCR0		0x800
50306fa012Schenhui zhao #define EPCCR15		0x83C
51306fa012Schenhui zhao #define EPCCR31		0x87C
52306fa012Schenhui zhao #define EPCCR_STRIDE	FSL_STRIDE_4B
53306fa012Schenhui zhao 
54306fa012Schenhui zhao /* EPCMPR0-15 (Event Processor Counter Compare Registers) */
55306fa012Schenhui zhao #define EPCMPR0		0x900
56306fa012Schenhui zhao #define EPCMPR15	0x93C
57306fa012Schenhui zhao #define EPCMPR31	0x97C
58306fa012Schenhui zhao #define EPCMPR_STRIDE	FSL_STRIDE_4B
59306fa012Schenhui zhao 
60306fa012Schenhui zhao /* EPCTR0-31 (Event Processor Counter Register) */
61306fa012Schenhui zhao #define EPCTR0		0xA00
62306fa012Schenhui zhao #define EPCTR31		0xA7C
63306fa012Schenhui zhao #define EPCTR_STRIDE	FSL_STRIDE_4B
64306fa012Schenhui zhao 
65d7b00639SHongbo Zhang #define FSM_END_FLAG	0xFFFFFFFFUL
66d7b00639SHongbo Zhang 
67d7b00639SHongbo Zhang struct fsm_reg_vals {
68d7b00639SHongbo Zhang 	u32 offset;
69d7b00639SHongbo Zhang 	u32 value;
70d7b00639SHongbo Zhang };
71d7b00639SHongbo Zhang 
72d7b00639SHongbo Zhang void fsl_epu_setup(void *epu_base);
73306fa012Schenhui zhao void fsl_epu_clean(void *epu_base);
74306fa012Schenhui zhao 
75306fa012Schenhui zhao #endif
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