Searched refs:EPECR0 (Results 1 – 3 of 3) sorted by relevance
| /openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | fsl_epu.c | 15 {EPECR0 + EPECR_STRIDE * 0, 0},
16 {EPECR0 + EPECR_STRIDE * 1, 0},
17 {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
18 {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
19 {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
20 {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
21 {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
22 {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
23 {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
24 {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
[all …]
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| H A D | ls102xa_psci.c | 53 out_be32(dcsr_epu_base + EPECR0, 0x5); in ls1_fsm_setup()
128 out_be32(dcsr_epu_base + EPECR0, 0x0); in ls1_start_fsm()
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| H A D | fsl_epu.h | 39 #define EPECR0 0x300 macro
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