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Searched refs:EMC_CFG (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/arch/arm/mach-tegra/
H A Dsleep-tegra30.S18 #define EMC_CFG 0xc macro
502 ldr r1, [r0, #EMC_CFG]
504 str r1, [r0, #EMC_CFG]
570 ldr r1, [r5, #0x0] @ restore EMC_CFG
571 str r1, [r0, #EMC_CFG]
592 .word TEGRA_EMC_BASE + EMC_CFG @0x0
603 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
611 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
619 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
831 ldr r1, [r0, #EMC_CFG]
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H A Dsleep-tegra20.S23 #define EMC_CFG 0xc macro
238 ldr r1, [r0, #EMC_CFG]
240 str r1, [r0, #EMC_CFG]
/openbmc/linux/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c501 emc_cfg_o = emc_readl(emc, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
510 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
565 emc_writel(emc, emc_cfg_o, EMC_CFG); in tegra210_emc_r21021_periodic_compensation()
648 emc_readl(emc, EMC_CFG); in tegra210_emc_r21021_set_clock()
720 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_set_clock()
752 emc_writel(emc, emc_cfg, EMC_CFG); in tegra210_emc_r21021_set_clock()
1025 if (offset == EMC_CFG) { in tegra210_emc_r21021_set_clock()
1612 EMC_CFG, 0); in tegra210_emc_r21021_set_clock()
1708 emc_writel(emc, next->burst_regs[EMC_CFG_INDEX], EMC_CFG); in tegra210_emc_r21021_set_clock()
H A Dtegra124-emc.c39 #define EMC_CFG 0xc macro
620 val = readl(emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
623 writel(val, emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
706 emc_ccfifo_writel(emc, val, EMC_CFG); in tegra_emc_prepare_timing_change()
843 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
889 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
H A Dtegra30-emc.c44 #define EMC_CFG 0x00c macro
554 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG); in emc_prepare_timing_change()
579 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
692 emc->regs + EMC_CFG); in emc_prepare_timing_change()
726 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
821 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_complete_timing_change()
H A Dtegra210-emc.h26 #define EMC_CFG 0xc macro
H A Dtegra210-emc-core.c245 EMC_CFG,
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml104 value of the EMC_CFG register for this set of timings