Home
last modified time | relevance | path

Searched refs:DSPSURF (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Di9xx_plane.c495 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i9xx_plane_update_arm()
538 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); in i9xx_plane_disable_arm()
559 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in g4x_primary_async_flip()
1026 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; in i9xx_get_initial_plane_config()
1034 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; in i9xx_get_initial_plane_config()
H A Dintel_fbc.c362 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), in i965_fbc_nuke()
363 intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane))); in i965_fbc_nuke()
/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_clock_gating.c147 intel_uncore_rmw(&dev_priv->uncore, DSPSURF(pipe), 0, 0); in g4x_disable_trickle_feed()
148 intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe)); in g4x_disable_trickle_feed()
H A Dintel_gvt_mmio_table.c165 MMIO_D(DSPSURF(PIPE_A)); in iterate_generic_mmio()
174 MMIO_D(DSPSURF(PIPE_B)); in iterate_generic_mmio()
183 MMIO_D(DSPSURF(PIPE_C)); in iterate_generic_mmio()
H A Di915_reg.h3163 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) macro
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dfb_decoder.c248 plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_primary_plane()
H A Dhandlers.c1006 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
2274 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2277 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2280 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
H A Dcmd_parser.c1318 info->surf_reg = DSPSURF(info->pipe); in gen8_decode_mi_display_flip()
1384 info->surf_reg = DSPSURF(info->pipe); in skl_decode_mi_display_flip()