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Searched refs:DSPCNTR (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Di9xx_plane.c492 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_plane_update_arm()
535 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in i9xx_plane_disable_arm()
557 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); in g4x_primary_async_flip()
681 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_plane_get_hw_state()
1004 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_get_initial_plane_config()
H A Dintel_display.c2880 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); in i9xx_get_pipe_color_config()
7980 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); in i830_disable_pipe()
7982 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); in i830_disable_pipe()
7984 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); in i830_disable_pipe()
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c192 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
503 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
H A Dfb_decoder.c214 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); in intel_vgpu_decode_primary_plane()
H A Dcmd_parser.c1316 info->ctrl_reg = DSPCNTR(info->pipe); in gen8_decode_mi_display_flip()
1382 info->ctrl_reg = DSPCNTR(info->pipe); in skl_decode_mi_display_flip()
H A Dhandlers.c1020 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) in pri_surf_mmio_write()
/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c160 MMIO_D(DSPCNTR(PIPE_A)); in iterate_generic_mmio()
169 MMIO_D(DSPCNTR(PIPE_B)); in iterate_generic_mmio()
178 MMIO_D(DSPCNTR(PIPE_C)); in iterate_generic_mmio()
H A Dintel_clock_gating.c145 intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(pipe), 0, DISP_TRICKLE_FEED_DISABLE); in g4x_disable_trickle_feed()
H A Di915_reg.h3158 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) macro