DRAMTMG5_TCKESR (reference) in projects: openbmc

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Searched refs:DRAMTMG5_TCKESR (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/
H A D	ddr2_v3s.c	`67 DRAMTMG5_TCKESR(tckesr) \| DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()`
H A D	lpddr3_stock.c	`66 DRAMTMG5_TCKESR(tckesr) \| DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()`
H A D	ddr3_1333.c	`70 DRAMTMG5_TCKESR(tckesr) \| DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()`
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A D	dram_sunxi_dw.h	`179 #define DRAMTMG5_TCKESR(x) ((x) << 8) macro`

Last Index Update: Fri Jul 05 03:03:48 CDT 2024