Home
last modified time | relevance | path

Searched refs:DRAMTMG2_TRD2WR (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/
H A Dddr2_v3s.c60 DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), in mctl_set_timing_params()
H A Dlpddr3_stock.c59 DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), in mctl_set_timing_params()
H A Dddr3_1333.c63 DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), in mctl_set_timing_params()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sunxi_dw.h165 #define DRAMTMG2_TRD2WR(x) ((x) << 8) macro