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Searched refs:DQ_NUM (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c125 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_tx()
265 [((pup) * DQ_NUM) + in ddr3_pbs_tx()
280 [((pup) * DQ_NUM) + dq]; in ddr3_pbs_tx()
338 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_tx()
568 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_rx()
654 DQ_NUM, CS0, in ddr3_pbs_rx()
711 dq < DQ_NUM; dq++) in ddr3_pbs_rx()
777 DQ_NUM) + in ddr3_pbs_rx()
854 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_rx()
1338 DQ_NUM) + in ddr3_pbs_per_bit()
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H A Dddr3_patterns_64bit.h61 u32 killer_pattern_32b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
336 u32 killer_pattern_64b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
611 u32 special_pattern[DQ_NUM][LEN_SPECIAL_PATTERN] __aligned(32) = {
911 u32 pbs_dq_mapping[PUP_NUM_64BIT + 1][DQ_NUM] = {
H A Dddr3_dqs.c82 extern int per_bit_data[MAX_PUP_NUM][DQ_NUM];
314 u8 analog_pbs[DQ_NUM][MAX_PUP_NUM][DQ_NUM][2]; in ddr3_find_adll_limits()
346 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_find_adll_limits()
378 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_find_adll_limits()
462 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_find_adll_limits()
542 dq < DQ_NUM; in ddr3_find_adll_limits()
577 for (dq = 0; dq < DQ_NUM; in ddr3_find_adll_limits()
668 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_find_adll_limits()
738 DQ_NUM * pup), 2); in ddr3_find_adll_limits()
775 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_find_adll_limits()
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H A Dddr3_sdram.c24 extern u32 pbs_dq_mapping[PUP_NUM_64BIT][DQ_NUM];
28 u32 pbs_locked_dq[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
30 u32 pbs_locked_value[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
32 int per_bit_data[MAX_PUP_NUM][DQ_NUM];
114 for (dq = 0; dq < DQ_NUM; dq++) { in compare_pattern_v1()
287 u32 pbs_write_pup[DQ_NUM] = { 0 }; in ddr3_sdram_pbs_compare()
363 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_sdram_pbs_compare()
392 skew_array[tmp_pup * DQ_NUM + dq] = in ddr3_sdram_pbs_compare()
404 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_sdram_pbs_compare()
H A Dddr3_hw_training.h136 #define DQ_NUM 8 macro
H A Dddr3_hw_training.c738 for (dq = 0; dq <= DQ_NUM; in ddr3_save_training()
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_patterns_64bit.h62 u32 killer_pattern_32b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
337 u32 killer_pattern_64b[DQ_NUM][LEN_KILLER_PATTERN] __aligned(32) = {
612 u32 special_pattern[DQ_NUM][LEN_SPECIAL_PATTERN] __aligned(32) = {
912 u32 pbs_dq_mapping[PUP_NUM_64BIT + 1][DQ_NUM] = {