Searched refs:DIVM (Results 1 – 3 of 3) sorted by relevance
71 ---->| / DIVM |---->| x DIVN | ------> VCO80 - VCO = ( Vref / DIVM ) * DIVN83 - VCO = ( Vref / DIVM ) * ( DIVN + FRACN / 2^13)94 - st,clock-div: DIVM division factor : <1..63>108 - 0: The PLL input (Vref / DIVM) clock range frequency is between 1 and 2 MHz109 - 1: The PLL input (Vref / DIVM) clock range frequency is between 2 and 4 MHz110 - 2: The PLL input (Vref / DIVM) clock range frequency is between 4 and 8 MHz111 - 3: The PLL input (Vref / DIVM) clock range frequency is between 8 and 16 MHz
59 DIVM DIVN DIVP DIVQ DIVR Output
29 DIVM, enumerator181 clk->p[DIVM] = m_table[m]; in plltv_integer_div()283 clk->p[DIVM] = m; in plltv_fractional_div()324 r2 |= HWM_FIELD_PREP(MASK_DIVM, clk->p[DIVM] - 1); in plltv_set_rate()