Searched refs:DISP_CC_MDSS_BYTE0_CLK (Results 1 – 25 of 52) sorted by relevance
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/openbmc/linux/include/dt-bindings/clock/ |
H A D | qcom,sm6115-dispcc.h | 14 #define DISP_CC_MDSS_BYTE0_CLK 4 macro
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H A D | qcom,dispcc-qcm2290.h | 13 #define DISP_CC_MDSS_BYTE0_CLK 3 macro
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H A D | qcom,sm6375-dispcc.h | 14 #define DISP_CC_MDSS_BYTE0_CLK 3 macro
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H A D | qcom,dispcc-sm6125.h | 12 #define DISP_CC_MDSS_BYTE0_CLK 3 macro
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H A D | qcom,dispcc-sc7180.h | 13 #define DISP_CC_MDSS_BYTE0_CLK 4 macro
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H A D | qcom,dispcc-sm6350.h | 14 #define DISP_CC_MDSS_BYTE0_CLK 3 macro
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H A D | qcom,dispcc-sdm845.h | 12 #define DISP_CC_MDSS_BYTE0_CLK 2 macro
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H A D | qcom,dispcc-sc7280.h | 13 #define DISP_CC_MDSS_BYTE0_CLK 3 macro
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H A D | qcom,dispcc-sm8150.h | 12 #define DISP_CC_MDSS_BYTE0_CLK 2 macro
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H A D | qcom,dispcc-sm8250.h | 12 #define DISP_CC_MDSS_BYTE0_CLK 2 macro
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H A D | qcom,dispcc-sm8350.h | 12 #define DISP_CC_MDSS_BYTE0_CLK 2 macro
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H A D | qcom,dispcc-sc8280xp.h | 17 #define DISP_CC_MDSS_BYTE0_CLK 7 macro
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H A D | qcom,sm8550-dispcc.h | 14 #define DISP_CC_MDSS_BYTE0_CLK 4 macro
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H A D | qcom,sm8450-dispcc.h | 13 #define DISP_CC_MDSS_BYTE0_CLK 3 macro
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/openbmc/linux/Documentation/devicetree/bindings/display/msm/ |
H A D | qcom,qcm2290-mdss.yaml | 140 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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H A D | qcom,sm6375-mdss.yaml | 146 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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H A D | qcom,sm6125-mdss.yaml | 148 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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H A D | qcom,sm6115-mdss.yaml | 130 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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H A D | qcom,sm6350-mdss.yaml | 145 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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H A D | qcom,sm8350-mdss.yaml | 187 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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H A D | qcom,sdm845-mdss.yaml | 148 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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H A D | qcom,sc7180-mdss.yaml | 156 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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H A D | qcom,sm8150-mdss.yaml | 179 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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H A D | qcom,sm8250-mdss.yaml | 181 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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H A D | qcom,sm8550-mdss.yaml | 190 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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