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Searched refs:DIDT_SQ_CTRL0__PHASE_OFFSET_MASK (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_powertune.c144 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
286 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
428 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
570 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
751 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
H A Dvega10_powertune.c206 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFF…
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h18271 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc macro
H A Dgfx_8_0_sh_mask.h20489 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc macro
H A Dgfx_8_1_sh_mask.h21091 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h28748 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK … macro
H A Dgc_9_2_1_sh_mask.h30291 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK … macro
H A Dgc_9_1_sh_mask.h29968 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK … macro
H A Dgc_9_4_2_sh_mask.h43 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK … macro
H A Dgc_10_1_0_sh_mask.h43084 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK … macro
H A Dgc_10_3_0_sh_mask.h48297 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK … macro