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Searched refs:DIDT_DB_CTRL0__PHASE_OFFSET_MASK (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_powertune.c242 …{ ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__PHASE_OFFSET_MASK, DIDT_DB_CTRL0__PHASE_OFF…
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h18315 #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc macro
H A Dgfx_8_0_sh_mask.h20543 #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc macro
H A Dgfx_8_1_sh_mask.h21147 #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h29003 #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK … macro
H A Dgc_9_2_1_sh_mask.h30508 #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK … macro
H A Dgc_9_1_sh_mask.h30218 #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK … macro
H A Dgc_9_4_2_sh_mask.h299 #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK … macro
H A Dgc_10_1_0_sh_mask.h43358 #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK … macro
H A Dgc_10_3_0_sh_mask.h48571 #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK … macro