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Searched refs:DDR_REG_SEQ2CORE (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/drivers/ddr/altera/
H A Dsdram_arria10.c30 #define DDR_REG_SEQ2CORE 0xFFD0507C macro
109 return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, in emif_clear()
119 s2c = readl(DDR_REG_SEQ2CORE); in emif_reset()
137 ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, in emif_reset()