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Searched refs:DDR_REG_CORE2SEQ (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/drivers/ddr/altera/
H A Dsdram_arria10.c31 #define DDR_REG_CORE2SEQ 0xFFD05078 macro
107 writel(0, DDR_REG_CORE2SEQ); in emif_clear()
118 c2s = readl(DDR_REG_CORE2SEQ); in emif_reset()
135 writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ); in emif_reset()