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Searched refs:DDRC1 (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp15-ddr.dtsi17 <&rcc DDRC1>,
/openbmc/linux/include/dt-bindings/clock/
H A Dstm32mp13-clks.h178 #define DDRC1 146 macro
H A Dstm32mp1-clks.h236 #define DDRC1 220 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dstm32mp1-clks.h236 #define DDRC1 220 macro
/openbmc/u-boot/doc/
H A DREADME.b4860qds65 - DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 4 GB
194 0x0_8000_0000 0x0_FFFF_FFFF DDRC1 2 GB
224 0x0_0000_0000 0x0_FFFF_FFFF DDRC1 4 GB
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dst,stm32mp1-ddr.txt162 <&rcc_clk DDRC1>,
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32mp1.c497 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),