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Searched refs:DDR4 (Results 1 – 25 of 34) sorted by relevance

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/openbmc/u-boot/drivers/ram/aspeed/
H A DKconfig5 prompt "DDR4 target data rate"
9 bool "DDR4 targets at 400Mbps"
12 select DDR4 target data rate at 400M
15 bool "DDR4 targets at 800Mbps"
18 select DDR4 target data rate at 800M
21 bool "DDR4 targets at 1333Mbps"
24 select DDR4 target data rate at 1333M
27 bool "DDR4 targets at 1600Mbps"
30 select DDR4 target data rate at 1600M
34 bool "dual X8 DDR4 die"
[all …]
/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Dmemory.hpp25 DDR4, enumerator
131 {MemoryDeviceType::DDR4, "DDR4"},
H A Dprocessor.hpp75 DDR4, enumerator
188 {ProcessorMemoryType::DDR4, "DDR4"},
/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A DKconfig14 Select the i.MX8M DDR4 driver support on i.MX8M SOC.
/openbmc/u-boot/drivers/ddr/fsl/
H A DKconfig104 Enable Freescale DDR4 controller.
126 bool "Freescale DDR4 controller"
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
66 - 1 64-bit DDR4 SDRAM memory controller with ECC
93 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
94 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
178 - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
220 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
221 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
289 Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC.
/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
88 - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
90 - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
124 - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
215 or make T1024QDS_D4_defconfig (For DDR4)
/openbmc/u-boot/board/freescale/ls1088a/
H A DREADME48 - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
114 - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
/openbmc/u-boot/board/freescale/ls2080ardb/
H A DREADME23 - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
25 - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
/openbmc/u-boot/board/freescale/ls1043ardb/
H A DREADME22 - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
/openbmc/u-boot/board/freescale/ls1043aqds/
H A DREADME23 - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s
/openbmc/u-boot/board/freescale/ls1046aqds/
H A DREADME23 - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
/openbmc/u-boot/board/freescale/ls1046ardb/
H A DREADME27 - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
/openbmc/u-boot/board/freescale/ls2080aqds/
H A DREADME24 - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
26 - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME17 - Support of DDR4 memory and some enhancements
21 - Support of DDR4 memory
48 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dplatform.S152 #define CONFIG_DDR4_SUPPORT_HYNIX @ Enable this when Hynix DDR4 included in the BOM
690 mov r1, r3, lsr #24 @ Check DDR4
712 mov r1, r3, lsr #24 @ Check DDR4
957 ldr r2, =0x01000000 @ bit[24]=1 => DDR4
2057 tst r1, #0x10 @ bit[4]=1 => DDR4
2058 movne r10, #0x9A @ DDR4 min = 0x99 (0.30)
2162 tst r1, #0x10 @ bit[4]=1 => DDR4
2163 movne r10, #0x30 @ DDR4 min = 0.30
2164 moveq r10, #0x35 @ DDR4 min = 0.35
/openbmc/u-boot/board/amlogic/q200/
H A DREADME.khadas-vim29 - 2/3GB DDR4 SDRAM
H A DREADME.q2009 - 2/3GB DDR4 SDRAM
/openbmc/u-boot/arch/arm/dts/
H A Dk3-am654-base-board-ddr4-1600MHz.dtsi7 * Memory Type: DDR4
/openbmc/u-boot/board/amlogic/s400/
H A DREADME8 - 1GB DDR4 SDRAM
/openbmc/qemu/docs/system/arm/
H A Dnuvoton.rst47 * DDR4 memory controller (dummy interface indicating memory training is done)
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME36 - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME36 - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
107 - SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
/openbmc/smbios-mdr/include/
H A Ddimm.hpp232 {0x1a, DeviceType::DDR4}, {0x1b, DeviceType::LPDDR_SDRAM},

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