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Searched refs:DDR3PHY_CTRL_PHY_RESET (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos5_setup.h251 #define DDR3PHY_CTRL_PHY_RESET (1 << 0) macro
H A Ddmc_init_ddr3.c32 writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); in reset_phy_ctrl()