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Searched refs:DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dce80/
H A Dirq_service_dce80.c95 .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
97 DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
98 ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dce60/
H A Dirq_service_dce60.c104 .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
106 DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
107 ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c301 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; in dce_v8_0_hpd_init()
2999 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; in dce_v8_0_set_hpd_interrupt_state()
3004 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; in dce_v8_0_set_hpd_interrupt_state()
H A Ddce_v6_0.c309 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; in dce_v6_0_hpd_init()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h3899 #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK 0x00010000L macro
H A Ddce_8_0_sh_mask.h6199 #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK 0x10000 macro