14562236bSHarry Wentland /*
24562236bSHarry Wentland * Copyright 2012-15 Advanced Micro Devices, Inc.
34562236bSHarry Wentland *
44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a
54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"),
64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation
74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense,
84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the
94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions:
104562236bSHarry Wentland *
114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in
124562236bSHarry Wentland * all copies or substantial portions of the Software.
134562236bSHarry Wentland *
144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE.
214562236bSHarry Wentland *
224562236bSHarry Wentland * Authors: AMD
234562236bSHarry Wentland *
244562236bSHarry Wentland */
254562236bSHarry Wentland
264562236bSHarry Wentland #include "dm_services.h"
274562236bSHarry Wentland
284562236bSHarry Wentland #include "include/logger_interface.h"
294562236bSHarry Wentland
304562236bSHarry Wentland #include "irq_service_dce80.h"
314562236bSHarry Wentland #include "../dce110/irq_service_dce110.h"
324562236bSHarry Wentland
334562236bSHarry Wentland #include "dce/dce_8_0_d.h"
344562236bSHarry Wentland #include "dce/dce_8_0_sh_mask.h"
354562236bSHarry Wentland
364562236bSHarry Wentland #include "ivsrcid/ivsrcid_vislands30.h"
374562236bSHarry Wentland
38667e1498SAndrey Grodzovsky #include "dc_types.h"
39667e1498SAndrey Grodzovsky
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)404562236bSHarry Wentland static bool hpd_ack(
414562236bSHarry Wentland struct irq_service *irq_service,
424562236bSHarry Wentland const struct irq_source_info *info)
434562236bSHarry Wentland {
444562236bSHarry Wentland uint32_t addr = info->status_reg;
454562236bSHarry Wentland uint32_t value = dm_read_reg(irq_service->ctx, addr);
464562236bSHarry Wentland uint32_t current_status =
474562236bSHarry Wentland get_reg_field_value(
484562236bSHarry Wentland value,
494562236bSHarry Wentland DC_HPD1_INT_STATUS,
504562236bSHarry Wentland DC_HPD1_SENSE_DELAYED);
514562236bSHarry Wentland
524562236bSHarry Wentland dal_irq_service_ack_generic(irq_service, info);
534562236bSHarry Wentland
544562236bSHarry Wentland value = dm_read_reg(irq_service->ctx, info->enable_reg);
554562236bSHarry Wentland
564562236bSHarry Wentland set_reg_field_value(
574562236bSHarry Wentland value,
584562236bSHarry Wentland current_status ? 0 : 1,
594562236bSHarry Wentland DC_HPD1_INT_CONTROL,
604562236bSHarry Wentland DC_HPD1_INT_POLARITY);
614562236bSHarry Wentland
624562236bSHarry Wentland dm_write_reg(irq_service->ctx, info->enable_reg, value);
634562236bSHarry Wentland
644562236bSHarry Wentland return true;
654562236bSHarry Wentland }
664562236bSHarry Wentland
674562236bSHarry Wentland static const struct irq_source_info_funcs hpd_irq_info_funcs = {
684562236bSHarry Wentland .set = NULL,
694562236bSHarry Wentland .ack = hpd_ack
704562236bSHarry Wentland };
714562236bSHarry Wentland
724562236bSHarry Wentland static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
734562236bSHarry Wentland .set = NULL,
744562236bSHarry Wentland .ack = NULL
754562236bSHarry Wentland };
764562236bSHarry Wentland
774562236bSHarry Wentland static const struct irq_source_info_funcs pflip_irq_info_funcs = {
784562236bSHarry Wentland .set = NULL,
794562236bSHarry Wentland .ack = NULL
804562236bSHarry Wentland };
814562236bSHarry Wentland
824562236bSHarry Wentland static const struct irq_source_info_funcs vblank_irq_info_funcs = {
83667e1498SAndrey Grodzovsky .set = dce110_vblank_set,
844562236bSHarry Wentland .ack = NULL
854562236bSHarry Wentland };
864562236bSHarry Wentland
87d2574c33SMario Kleiner static const struct irq_source_info_funcs vupdate_irq_info_funcs = {
88d2574c33SMario Kleiner .set = NULL,
89d2574c33SMario Kleiner .ack = NULL
90d2574c33SMario Kleiner };
914562236bSHarry Wentland
924562236bSHarry Wentland #define hpd_int_entry(reg_num)\
934562236bSHarry Wentland [DC_IRQ_SOURCE_INVALID + reg_num] = {\
944562236bSHarry Wentland .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
954562236bSHarry Wentland .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
964562236bSHarry Wentland .enable_value = {\
974562236bSHarry Wentland DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
984562236bSHarry Wentland ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
994562236bSHarry Wentland },\
1004562236bSHarry Wentland .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
1014562236bSHarry Wentland .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
1024562236bSHarry Wentland .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
1034562236bSHarry Wentland .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
1044562236bSHarry Wentland .funcs = &hpd_irq_info_funcs\
1054562236bSHarry Wentland }
1064562236bSHarry Wentland
1074562236bSHarry Wentland #define hpd_rx_int_entry(reg_num)\
1084562236bSHarry Wentland [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
1094562236bSHarry Wentland .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
1104562236bSHarry Wentland .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
1114562236bSHarry Wentland .enable_value = {\
1124562236bSHarry Wentland DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
1134562236bSHarry Wentland ~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
1144562236bSHarry Wentland .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
1154562236bSHarry Wentland .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
1164562236bSHarry Wentland .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
1174562236bSHarry Wentland .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
1184562236bSHarry Wentland .funcs = &hpd_rx_irq_info_funcs\
1194562236bSHarry Wentland }
1204562236bSHarry Wentland
1214562236bSHarry Wentland #define pflip_int_entry(reg_num)\
1224562236bSHarry Wentland [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
1234562236bSHarry Wentland .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
1244562236bSHarry Wentland .enable_mask =\
1254562236bSHarry Wentland GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
1264562236bSHarry Wentland .enable_value = {\
1274562236bSHarry Wentland GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
1284562236bSHarry Wentland ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
1294562236bSHarry Wentland .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
1304562236bSHarry Wentland .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
1314562236bSHarry Wentland .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
1324562236bSHarry Wentland .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
1334562236bSHarry Wentland .funcs = &pflip_irq_info_funcs\
1344562236bSHarry Wentland }
1354562236bSHarry Wentland
1364562236bSHarry Wentland #define vupdate_int_entry(reg_num)\
1374562236bSHarry Wentland [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
1384562236bSHarry Wentland .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
1394562236bSHarry Wentland .enable_mask =\
1404562236bSHarry Wentland CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
1414562236bSHarry Wentland .enable_value = {\
1424562236bSHarry Wentland CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
1434562236bSHarry Wentland ~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
1444562236bSHarry Wentland .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
1454562236bSHarry Wentland .ack_mask =\
1464562236bSHarry Wentland CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
1474562236bSHarry Wentland .ack_value =\
1484562236bSHarry Wentland CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
149d2574c33SMario Kleiner .funcs = &vupdate_irq_info_funcs\
1504562236bSHarry Wentland }
1514562236bSHarry Wentland
152b10d51f8SAndrey Grodzovsky #define vblank_int_entry(reg_num)\
153b10d51f8SAndrey Grodzovsky [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
154667e1498SAndrey Grodzovsky .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
155b10d51f8SAndrey Grodzovsky .enable_mask =\
156667e1498SAndrey Grodzovsky CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
157b10d51f8SAndrey Grodzovsky .enable_value = {\
158667e1498SAndrey Grodzovsky CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
159667e1498SAndrey Grodzovsky ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
160667e1498SAndrey Grodzovsky .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
161b10d51f8SAndrey Grodzovsky .ack_mask =\
162667e1498SAndrey Grodzovsky CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
163b10d51f8SAndrey Grodzovsky .ack_value =\
164667e1498SAndrey Grodzovsky CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
165667e1498SAndrey Grodzovsky .funcs = &vblank_irq_info_funcs,\
166667e1498SAndrey Grodzovsky .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
167b10d51f8SAndrey Grodzovsky }
168b10d51f8SAndrey Grodzovsky
1694562236bSHarry Wentland #define dummy_irq_entry() \
1704562236bSHarry Wentland {\
1714562236bSHarry Wentland .funcs = &dummy_irq_info_funcs\
1724562236bSHarry Wentland }
1734562236bSHarry Wentland
1744562236bSHarry Wentland #define i2c_int_entry(reg_num) \
1754562236bSHarry Wentland [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
1764562236bSHarry Wentland
1774562236bSHarry Wentland #define dp_sink_int_entry(reg_num) \
1784562236bSHarry Wentland [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
1794562236bSHarry Wentland
1804562236bSHarry Wentland #define gpio_pad_int_entry(reg_num) \
1814562236bSHarry Wentland [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
1824562236bSHarry Wentland
1834562236bSHarry Wentland #define dc_underflow_int_entry(reg_num) \
1844562236bSHarry Wentland [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
1854562236bSHarry Wentland
1864562236bSHarry Wentland
1874562236bSHarry Wentland static const struct irq_source_info_funcs dummy_irq_info_funcs = {
1884562236bSHarry Wentland .set = dal_irq_service_dummy_set,
1894562236bSHarry Wentland .ack = dal_irq_service_dummy_ack
1904562236bSHarry Wentland };
1914562236bSHarry Wentland
1924562236bSHarry Wentland static const struct irq_source_info
1934562236bSHarry Wentland irq_source_info_dce80[DAL_IRQ_SOURCES_NUMBER] = {
1944562236bSHarry Wentland [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
1954562236bSHarry Wentland hpd_int_entry(1),
1964562236bSHarry Wentland hpd_int_entry(2),
1974562236bSHarry Wentland hpd_int_entry(3),
1984562236bSHarry Wentland hpd_int_entry(4),
1994562236bSHarry Wentland hpd_int_entry(5),
2004562236bSHarry Wentland hpd_int_entry(6),
2014562236bSHarry Wentland hpd_rx_int_entry(1),
2024562236bSHarry Wentland hpd_rx_int_entry(2),
2034562236bSHarry Wentland hpd_rx_int_entry(3),
2044562236bSHarry Wentland hpd_rx_int_entry(4),
2054562236bSHarry Wentland hpd_rx_int_entry(5),
2064562236bSHarry Wentland hpd_rx_int_entry(6),
2074562236bSHarry Wentland i2c_int_entry(1),
2084562236bSHarry Wentland i2c_int_entry(2),
2094562236bSHarry Wentland i2c_int_entry(3),
2104562236bSHarry Wentland i2c_int_entry(4),
2114562236bSHarry Wentland i2c_int_entry(5),
2124562236bSHarry Wentland i2c_int_entry(6),
2134562236bSHarry Wentland dp_sink_int_entry(1),
2144562236bSHarry Wentland dp_sink_int_entry(2),
2154562236bSHarry Wentland dp_sink_int_entry(3),
2164562236bSHarry Wentland dp_sink_int_entry(4),
2174562236bSHarry Wentland dp_sink_int_entry(5),
2184562236bSHarry Wentland dp_sink_int_entry(6),
2194562236bSHarry Wentland [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
2204562236bSHarry Wentland pflip_int_entry(0),
2214562236bSHarry Wentland pflip_int_entry(1),
2224562236bSHarry Wentland pflip_int_entry(2),
2234562236bSHarry Wentland pflip_int_entry(3),
2244562236bSHarry Wentland pflip_int_entry(4),
2254562236bSHarry Wentland pflip_int_entry(5),
2264562236bSHarry Wentland [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
2274562236bSHarry Wentland gpio_pad_int_entry(0),
2284562236bSHarry Wentland gpio_pad_int_entry(1),
2294562236bSHarry Wentland gpio_pad_int_entry(2),
2304562236bSHarry Wentland gpio_pad_int_entry(3),
2314562236bSHarry Wentland gpio_pad_int_entry(4),
2324562236bSHarry Wentland gpio_pad_int_entry(5),
2334562236bSHarry Wentland gpio_pad_int_entry(6),
2344562236bSHarry Wentland gpio_pad_int_entry(7),
2354562236bSHarry Wentland gpio_pad_int_entry(8),
2364562236bSHarry Wentland gpio_pad_int_entry(9),
2374562236bSHarry Wentland gpio_pad_int_entry(10),
2384562236bSHarry Wentland gpio_pad_int_entry(11),
2394562236bSHarry Wentland gpio_pad_int_entry(12),
2404562236bSHarry Wentland gpio_pad_int_entry(13),
2414562236bSHarry Wentland gpio_pad_int_entry(14),
2424562236bSHarry Wentland gpio_pad_int_entry(15),
2434562236bSHarry Wentland gpio_pad_int_entry(16),
2444562236bSHarry Wentland gpio_pad_int_entry(17),
2454562236bSHarry Wentland gpio_pad_int_entry(18),
2464562236bSHarry Wentland gpio_pad_int_entry(19),
2474562236bSHarry Wentland gpio_pad_int_entry(20),
2484562236bSHarry Wentland gpio_pad_int_entry(21),
2494562236bSHarry Wentland gpio_pad_int_entry(22),
2504562236bSHarry Wentland gpio_pad_int_entry(23),
2514562236bSHarry Wentland gpio_pad_int_entry(24),
2524562236bSHarry Wentland gpio_pad_int_entry(25),
2534562236bSHarry Wentland gpio_pad_int_entry(26),
2544562236bSHarry Wentland gpio_pad_int_entry(27),
2554562236bSHarry Wentland gpio_pad_int_entry(28),
2564562236bSHarry Wentland gpio_pad_int_entry(29),
2574562236bSHarry Wentland gpio_pad_int_entry(30),
2584562236bSHarry Wentland dc_underflow_int_entry(1),
2594562236bSHarry Wentland dc_underflow_int_entry(2),
2604562236bSHarry Wentland dc_underflow_int_entry(3),
2614562236bSHarry Wentland dc_underflow_int_entry(4),
2624562236bSHarry Wentland dc_underflow_int_entry(5),
2634562236bSHarry Wentland dc_underflow_int_entry(6),
2644562236bSHarry Wentland [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
2654562236bSHarry Wentland [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
2664562236bSHarry Wentland vupdate_int_entry(0),
2674562236bSHarry Wentland vupdate_int_entry(1),
2684562236bSHarry Wentland vupdate_int_entry(2),
2694562236bSHarry Wentland vupdate_int_entry(3),
2704562236bSHarry Wentland vupdate_int_entry(4),
2714562236bSHarry Wentland vupdate_int_entry(5),
272b10d51f8SAndrey Grodzovsky vblank_int_entry(0),
273b10d51f8SAndrey Grodzovsky vblank_int_entry(1),
274b10d51f8SAndrey Grodzovsky vblank_int_entry(2),
275b10d51f8SAndrey Grodzovsky vblank_int_entry(3),
276b10d51f8SAndrey Grodzovsky vblank_int_entry(4),
277b10d51f8SAndrey Grodzovsky vblank_int_entry(5),
2784562236bSHarry Wentland };
2794562236bSHarry Wentland
2804562236bSHarry Wentland static const struct irq_service_funcs irq_service_funcs_dce80 = {
2814562236bSHarry Wentland .to_dal_irq_source = to_dal_irq_source_dce110
2824562236bSHarry Wentland };
2834562236bSHarry Wentland
dce80_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)284d9e32672SAnthony Koo static void dce80_irq_construct(
2854562236bSHarry Wentland struct irq_service *irq_service,
2864562236bSHarry Wentland struct irq_service_init_data *init_data)
2874562236bSHarry Wentland {
2886be663b5SDave Airlie dal_irq_service_construct(irq_service, init_data);
2894562236bSHarry Wentland
2904562236bSHarry Wentland irq_service->info = irq_source_info_dce80;
2914562236bSHarry Wentland irq_service->funcs = &irq_service_funcs_dce80;
2924562236bSHarry Wentland }
2934562236bSHarry Wentland
dal_irq_service_dce80_create(struct irq_service_init_data * init_data)2944562236bSHarry Wentland struct irq_service *dal_irq_service_dce80_create(
2954562236bSHarry Wentland struct irq_service_init_data *init_data)
2964562236bSHarry Wentland {
2972004f45eSHarry Wentland struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
2982004f45eSHarry Wentland GFP_KERNEL);
2994562236bSHarry Wentland
3004562236bSHarry Wentland if (!irq_service)
3014562236bSHarry Wentland return NULL;
3024562236bSHarry Wentland
303d9e32672SAnthony Koo dce80_irq_construct(irq_service, init_data);
3044562236bSHarry Wentland return irq_service;
3054562236bSHarry Wentland }
3064562236bSHarry Wentland
3074562236bSHarry Wentland
308