Searched refs:DCSR_RUN (Results 1 – 5 of 5) sorted by relevance
37 #define DCSR_RUN (1 << 0) macro205 dcsr = DCSR_STRTA | DCSR_IE | DCSR_RUN; in sa11x0_dma_start_sg()209 dcsr = DCSR_STRTB | DCSR_IE | DCSR_RUN; in sa11x0_dma_start_sg()316 writel_relaxed(DCSR_RUN | DCSR_STRTA | DCSR_STRTB, in sa11x0_dma_start_txd()714 writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_C); in sa11x0_dma_device_pause()740 writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_S); in sa11x0_dma_device_resume()769 writel(DCSR_RUN | DCSR_IE | in sa11x0_dma_device_terminate_all()939 writel_relaxed(DCSR_RUN | DCSR_IE | DCSR_ERROR | in sa11x0_dma_probe()1014 if (dcsr & DCSR_RUN) { in sa11x0_dma_suspend()1015 writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_C); in sa11x0_dma_suspend()[all …]
32 #define DCSR_RUN BIT(31) /* Run Bit (read / write) */ macro169 writel(readl(phy->base + reg) | DCSR_RUN, phy->base + reg); in enable_chan()180 writel(readl(phy->base + reg) & ~DCSR_RUN, phy->base + reg); in disable_chan()
118 #define DCSR_RUN (1 << 31) macro201 while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) { in pxa2xx_dma_run()251 ch->state &= ~DCSR_RUN; in pxa2xx_dma_run()371 if (value & DCSR_RUN) { in pxa2xx_dma_write()377 if (value & DCSR_RUN) { in pxa2xx_dma_write()385 if (!(value & (DCSR_RUN | DCSR_MASKRUN))) in pxa2xx_dma_write()
133 #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ macro
2541 #define DCSR_RUN 0x00000001 /* DMA RUNing */ macro