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/openbmc/qemu/tests/qemu-iotests/
H A D142.out38 Cache mode: writeback, direct
39 Cache mode: writeback, direct
40 Cache mode: writeback, direct
41 Cache mode: writeback, direct
42 Cache mode: writeback, direct
45 Cache mode: writeback
46 Cache mode: writeback
47 Cache mode: writeback, direct
48 Cache mode: writeback
49 Cache mode: writeback
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H A D157.out7 Cache mode: writeback
9 Cache mode: writeback
11 Cache mode: writeback
13 Cache mode: writethrough
15 Cache mode: writethrough
17 Cache mode: writethrough
19 Cache mode: writeback
21 Cache mode: writethrough
H A D186.out62 Cache mode: writeback
70 Cache mode: writeback
78 Cache mode: writeback
86 Cache mode: writeback
94 Cache mode: writeback
102 Cache mode: writeback
111 Cache mode: writeback
120 Cache mode: writeback
129 Cache mode: writeback
138 Cache mode: writeback
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H A D172.out66 Cache mode: writeback
119 Cache mode: writeback
176 Cache mode: writeback
181 Cache mode: writeback
263 Cache mode: writeback
316 Cache mode: writeback
373 Cache mode: writeback
378 Cache mode: writeback
420 Cache mode: writeback
459 Cache mode: writeback
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/openbmc/qemu/contrib/plugins/
H A Dcache.c81 } Cache; typedef
92 void (*update_hit)(Cache *cache, int set, int blk);
93 void (*update_miss)(Cache *cache, int set, int blk);
95 void (*metadata_init)(Cache *cache);
96 void (*metadata_destroy)(Cache *cache);
99 static Cache **l1_dcaches, **l1_icaches;
102 static Cache **l2_ucaches;
140 static void lru_priorities_init(Cache *cache) in lru_priorities_init()
150 static void lru_update_blk(Cache *cache, int set_idx, int blk_idx) in lru_update_blk()
157 static int lru_get_lru_block(Cache *cache, int set_idx) in lru_get_lru_block()
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/openbmc/qemu/target/hexagon/imported/
H A Dsystem.idef36 Q6INSN(Y2_icinva,"icinva(Rs32)",ATTRIBS(A_ICOP,A_ICFLUSHOP),"Instruction Cache Invalidate Address",…
43 Q6INSN(Y2_dcfetchbo,"dcfetch(Rs32+#u11:3)",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH),"Data Cache Pr…
47 Q6INSN(Y2_dccleana,"dccleana(Rs32)",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Clean Add…
48 Q6INSN(Y2_dccleaninva,"dccleaninva(Rs32)",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Cle…
49 Q6INSN(Y2_dcinva,"dcinva(Rs32)",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Invalidate Ad…
52 Q6INSN(Y4_l2fetch,"l2fetch(Rs32,Rt32)",ATTRIBS(A_RESTRICT_SLOT0ONLY),"L2 Cache Prefetch",
62 Q6INSN(Y5_l2fetch,"l2fetch(Rs32,Rtt32)",ATTRIBS(A_RESTRICT_SLOT0ONLY),"L2 Cache Prefetch",
/openbmc/u-boot/board/coreboot/coreboot/
H A DKconfig23 hex "Board specific Cache-As-RAM (CAR) address"
26 This option specifies the board specific Cache-As-RAM (CAR) address.
29 hex "Board specific Cache-As-RAM (CAR) size"
32 This option specifies the board specific Cache-As-RAM (CAR) size.
/openbmc/linux/Documentation/filesystems/caching/
H A Dfscache.rst13 FS-Cache mediates between cache backends (such as CacheFiles) and network
24 | AFS |----->| | | FS-Cache |
34 Or to look at it another way, FS-Cache is a module that provides a caching
50 | NFS |----->| FS-Cache |
71 FS-Cache does not follow the idea of completely loading every netfs file
91 FS-Cache provides the following facilities:
105 Cache cookies represent the cache as a whole and are not normally visible
145 The netfs API to FS-Cache can be found in:
149 The cache backend API to FS-Cache can be found in:
157 If FS-Cache is compiled with the following options enabled::
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/openbmc/qemu/util/
H A Dcacheflush.c53 && buf[i].Cache.Level == 1) { in sys_cache_info()
54 switch (buf[i].Cache.Type) { in sys_cache_info()
56 *isize = *dsize = buf[i].Cache.LineSize; in sys_cache_info()
59 *isize = buf[i].Cache.LineSize; in sys_cache_info()
62 *dsize = buf[i].Cache.LineSize; in sys_cache_info()
328 * POWER9 UM, 4.6.2.2 Instruction Cache Block Invalidate (icbi) in flush_idcache_range()
/openbmc/linux/Documentation/arch/xtensa/
H A Dmmu.rst86 | Cache aliasing | TLBTEMP_BASE_1 0xc8000000 DCACHE_WAY_SIZE
89 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
129 | Cache aliasing | TLBTEMP_BASE_1 0xa8000000 DCACHE_WAY_SIZE
132 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
173 | Cache aliasing | TLBTEMP_BASE_1 0x98000000 DCACHE_WAY_SIZE
176 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
/openbmc/u-boot/arch/powerpc/dts/
H A De6500_power_isa.dtsi15 power-isa-cs; // Cache Specification
23 power-isa-ecl; // Embedded Cache Locking
36 fsl,eref-deo; // Data Cache Extended Operations
/openbmc/linux/drivers/cache/
H A DKconfig2 menu "Cache Drivers"
5 bool "Andes Technology AX45MP L2 Cache controller"
/openbmc/u-boot/doc/
H A DREADME.N121333 - Cache size: 8KB/16KB/32KB/64KB.
34 - Cache line size: 16B/32B.
36 - Cache locking support.
/openbmc/entity-manager/src/
H A Dfru_reader.hpp56 using Cache = std::map<uint32_t, CacheBlock>; typedef in FRUReader
59 Cache cache;
/openbmc/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv92 4, 0, EAX, 4:0, cache_type, Cache type like instr/data or unified
93 4, 0, EAX, 7:5, cache_level, Cache Level (starts at 1)
94 4, 0, EAX, 8, cache_self_init, Cache Self Initialization
106 4, 0, EDX, 2, c_comp_index, Complex Cache Indexing
207 # Direct Cache Access (DCA) information
271 0xF, 0, EDX, 1, l3c_rdt_mon, L3 Cache RDT Monitoring supported
274 0xF, 1, EDX, 0, l3c_ocp_mon, L3 Cache occupancy Monitoring supported
275 0xF, 1, EDX, 1, l3c_tbw_mon, L3 Cache Total Bandwidth Monitoring supported
276 0xF, 1, EDX, 2, l3c_lbw_mon, L3 Cache Local Bandwidth Monitoring supported
281 0x10, 0, EBX, 1, l3c_rdt_alloc, L3 Cache Allocation supported
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmvebu-core-clock.txt10 2 = nbclk (L2 Cache clock)
17 2 = l2clk (L2 Cache clock)
23 2 = l2clk (L2 Cache clock)
43 2 = l2clk (L2 Cache clock derived from CPU0 clock)
/openbmc/u-boot/board/renesas/MigoR/
H A Dlowlevel_init.S31 write32 CCR_A, CCR_D ! Address of Cache Control Register
32 ! Instruction Cache Invalidate
64 write32 CCR_A, CCR_D_2 ! Address of Cache Control Register
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A De500mc_power_isa.dtsi41 power-isa-cs; // Cache Specification
49 power-isa-ecl; // Embedded Cache Locking
56 fsl,eref-deo; // Data Cache Extended Operations
H A De5500_power_isa.dtsi41 power-isa-cs; // Cache Specification
49 power-isa-ecl; // Embedded Cache Locking
57 fsl,eref-deo; // Data Cache Extended Operations
/openbmc/qemu/qapi/
H A Dmachine-common.json86 # Cache information for SMP system.
88 # @cache: Cache name, which is the combination of cache level
91 # @topology: Cache topology level. It accepts the CPU topology
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME30 - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)
31 - 512 Kbyte shared coherent L2 Cache (with ECC protection)
35 - ARM Core-Link CCI-400 Cache Coherent Interconnect
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME30 - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)
31 - 512 Kbyte shared coherent L2 Cache (with ECC protection)
35 - ARM Core-Link CCI-400 Cache Coherent Interconnect
/openbmc/linux/arch/nios2/platform/
H A DKconfig.platform115 comment "Cache settings"
128 hex "D-Cache size" if CUSTOM_CACHE_SETTINGS
135 hex "D-Cache line size" if CUSTOM_CACHE_SETTINGS
142 hex "I-Cache size" if CUSTOM_CACHE_SETTINGS
/openbmc/
Dopengrok0.0.log[all...]
/openbmc/qemu/docs/system/arm/
H A Demulation.rst32 - FEAT_CSV2 (Cache speculation variant 2)
33 - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
34 - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
35 - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
36 - FEAT_CSV2_3 (Cache speculation variant 2, version 3)
37 - FEAT_CSV3 (Cache speculation variant 3)

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