| /openbmc/qemu/tests/qemu-iotests/ |
| H A D | 142.out | 38 Cache mode: writeback, direct
39 Cache mode: writeback, direct
40 Cache mode: writeback, direct
41 Cache mode: writeback, direct
42 Cache mode: writeback, direct
45 Cache mode: writeback
46 Cache mode: writeback
47 Cache mode: writeback, direct
48 Cache mode: writeback
49 Cache mode: writeback
[all …]
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| H A D | 157.out | 7 Cache mode: writeback
9 Cache mode: writeback
11 Cache mode: writeback
13 Cache mode: writethrough
15 Cache mode: writethrough
17 Cache mode: writethrough
19 Cache mode: writeback
21 Cache mode: writethrough
|
| H A D | 186.out | 62 Cache mode: writeback
70 Cache mode: writeback
78 Cache mode: writeback
86 Cache mode: writeback
94 Cache mode: writeback
102 Cache mode: writeback
111 Cache mode: writeback
120 Cache mode: writeback
129 Cache mode: writeback
138 Cache mode: writeback
[all …]
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| H A D | 172.out | 66 Cache mode: writeback
116 Cache mode: writeback
170 Cache mode: writeback
175 Cache mode: writeback
254 Cache mode: writeback
304 Cache mode: writeback
358 Cache mode: writeback
363 Cache mode: writeback
402 Cache mode: writeback
438 Cache mode: writeback
[all …]
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| H A D | 051.out | 87 Cache mode: writeback
150 === Cache modes ===
180 Cache mode: writeback
185 Cache mode: writeback
188 Cache mode: writeback, ignore flushes
192 Cache mode: writeback, ignore flushes
200 Cache mode: writethrough
205 Cache mode: writeback
208 Cache mode: writeback, ignore flushes
212 Cache mode: writeback, ignore flushes
[all …]
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| /openbmc/qemu/contrib/plugins/ |
| H A D | cache.c | 81 } Cache; typedef
92 void (*update_hit)(Cache *cache, int set, int blk);
93 void (*update_miss)(Cache *cache, int set, int blk);
95 void (*metadata_init)(Cache *cache);
96 void (*metadata_destroy)(Cache *cache);
99 static Cache **l1_dcaches, **l1_icaches;
102 static Cache **l2_ucaches;
140 static void lru_priorities_init(Cache *cache) in lru_priorities_init()
150 static void lru_update_blk(Cache *cache, int set_idx, int blk_idx) in lru_update_blk()
157 static int lru_get_lru_block(Cache *cache, int set_idx) in lru_get_lru_block()
[all …]
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| /openbmc/u-boot/board/coreboot/coreboot/ |
| H A D | Kconfig | 23 hex "Board specific Cache-As-RAM (CAR) address"
26 This option specifies the board specific Cache-As-RAM (CAR) address.
29 hex "Board specific Cache-As-RAM (CAR) size"
32 This option specifies the board specific Cache-As-RAM (CAR) size.
|
| /openbmc/qemu/target/hexagon/imported/ |
| H A D | system.idef | 36 Q6INSN(Y2_icinva,"icinva(Rs32)",ATTRIBS(A_ICOP,A_ICFLUSHOP),"Instruction Cache Invalidate Address",…
43 Q6INSN(Y2_dcfetchbo,"dcfetch(Rs32+#u11:3)",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH),"Data Cache Pr…
47 Q6INSN(Y2_dccleana,"dccleana(Rs32)",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Clean Add…
48 Q6INSN(Y2_dccleaninva,"dccleaninva(Rs32)",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Cle…
49 Q6INSN(Y2_dcinva,"dcinva(Rs32)",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Invalidate Ad…
52 Q6INSN(Y4_l2fetch,"l2fetch(Rs32,Rt32)",ATTRIBS(A_RESTRICT_SLOT0ONLY),"L2 Cache Prefetch",
62 Q6INSN(Y5_l2fetch,"l2fetch(Rs32,Rtt32)",ATTRIBS(A_RESTRICT_SLOT0ONLY),"L2 Cache Prefetch",
|
| /openbmc/entity-manager/src/fru_device/ |
| H A D | fru_reader.hpp | 43 using Cache = std::map<uint32_t, CacheBlock>; typedef in FRUReader
46 Cache cache;
|
| /openbmc/qemu/util/ |
| H A D | cacheflush.c | 53 && buf[i].Cache.Level == 1) { in sys_cache_info()
54 switch (buf[i].Cache.Type) { in sys_cache_info()
56 *isize = *dsize = buf[i].Cache.LineSize; in sys_cache_info()
59 *isize = buf[i].Cache.LineSize; in sys_cache_info()
62 *dsize = buf[i].Cache.LineSize; in sys_cache_info()
|
| /openbmc/u-boot/arch/powerpc/dts/ |
| H A D | e6500_power_isa.dtsi | 15 power-isa-cs; // Cache Specification
23 power-isa-ecl; // Embedded Cache Locking
36 fsl,eref-deo; // Data Cache Extended Operations
|
| /openbmc/u-boot/doc/ |
| H A D | README.N1213 | 33 - Cache size: 8KB/16KB/32KB/64KB.
34 - Cache line size: 16B/32B.
36 - Cache locking support.
|
| H A D | README.mips | 19 * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c
21 Cache will be disabled before entering the loaded ELF image without
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| /openbmc/u-boot/board/renesas/MigoR/ |
| H A D | lowlevel_init.S | 31 write32 CCR_A, CCR_D ! Address of Cache Control Register
32 ! Instruction Cache Invalidate
64 write32 CCR_A, CCR_D_2 ! Address of Cache Control Register
|
| /openbmc/qemu/qapi/ |
| H A D | machine-common.json | 88 # Cache information for SMP system.
90 # @cache: Cache name, which is the combination of cache level
93 # @topology: Cache topology level. It accepts the CPU topology
|
| /openbmc/u-boot/board/freescale/ls1021atwr/ |
| H A D | README | 30 - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)
31 - 512 Kbyte shared coherent L2 Cache (with ECC protection)
35 - ARM Core-Link CCI-400 Cache Coherent Interconnect
|
| /openbmc/u-boot/board/freescale/ls1021aqds/ |
| H A D | README | 30 - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)
31 - 512 Kbyte shared coherent L2 Cache (with ECC protection)
35 - ARM Core-Link CCI-400 Cache Coherent Interconnect
|
| /openbmc/openbmc/meta-openembedded/meta-python/recipes-devtools/python/ |
| H A D | python3-diskcache_5.6.3.bb | 1 DESCRIPTION = "Disk Cache -- Disk and file backed persistent cache."
|
| /openbmc/qemu/docs/system/arm/ |
| H A D | emulation.rst | 33 - FEAT_CSV2 (Cache speculation variant 2)
34 - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
35 - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
36 - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
37 - FEAT_CSV2_3 (Cache speculation variant 2, version 3)
38 - FEAT_CSV3 (Cache speculation variant 3)
|
| /openbmc/bmcweb/redfish-core/include/generated/enums/ |
| H A D | memory.hpp | 17 Cache, enumerator
123 {MemoryType::Cache, "Cache"},
|
| H A D | processor.hpp | 51 Cache, enumerator
164 {ProcessorMemoryType::Cache, "Cache"},
|
| /openbmc/ |
| D | opengrok0.0.log | [all...] |
| /openbmc/u-boot/arch/x86/cpu/tangier/ |
| H A D | Kconfig | 27 Space in bytes in eSRAM used as Cache-As-RAM (CAR).
|
| /openbmc/u-boot/arch/arm/cpu/arm1136/ |
| H A D | start.S | 81 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
|
| /openbmc/phosphor-fan-presence/docs/control/ |
| H A D | debug.md | 23 ## Object Cache
80 ## Service Cache
|