Home
last modified time | relevance | path

Searched refs:C_O1_I1 (Results 1 – 21 of 21) sorted by relevance

/openbmc/qemu/tcg/i386/
H A Dtcg-target-con-set.h30 C_O1_I1(r, 0)
31 C_O1_I1(r, L)
32 C_O1_I1(r, q)
33 C_O1_I1(r, r)
34 C_O1_I1(x, r)
35 C_O1_I1(x, x)
H A Dtcg-target.c.inc3631 return C_O1_I1(r, r);
3696 return C_O1_I1(r, 0);
3702 return C_O1_I1(r, q);
3718 return C_O1_I1(r, r);
3765 return C_O1_I1(r, L);
3767 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O1_I2(r, L, L);
3779 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O2_I1(r, r, L);
3781 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O2_I2(r, r, L, L);
3805 return C_O1_I1(x, r);
3859 return C_O1_I1(x, x);
/openbmc/qemu/tcg/arm/
H A Dtcg-target-con-set.h21 C_O1_I1(r, q)
22 C_O1_I1(r, r)
23 C_O1_I1(w, r)
24 C_O1_I1(w, w)
25 C_O1_I1(w, wr)
H A Dtcg-target.c.inc2141 return C_O1_I1(r, r);
2198 return C_O1_I1(r, q);
2218 return C_O1_I1(w, r);
2220 return C_O1_I1(w, wr);
2227 return C_O1_I1(w, w);
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target-con-set.h17 C_O1_I1(r, r)
18 C_O1_I1(w, r)
19 C_O1_I1(w, w)
20 C_O1_I1(w, wr)
H A Dtcg-target.c.inc2997 return C_O1_I1(r, r);
3078 return C_O1_I1(r, r);
3128 return C_O1_I1(w, w);
3131 return C_O1_I1(w, r);
3135 return C_O1_I1(w, wr);
/openbmc/qemu/tcg/ppc/
H A Dtcg-target-con-set.h20 C_O1_I1(r, r)
21 C_O1_I1(v, r)
22 C_O1_I1(v, v)
23 C_O1_I1(v, vr)
H A Dtcg-target.c.inc4183 return C_O1_I1(r, r);
4281 return C_O1_I1(r, r);
4283 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r);
4285 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r);
4287 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r);
4340 return C_O1_I1(v, v);
4343 return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v);
4347 return C_O1_I1(v, r);
/openbmc/qemu/tcg/s390x/
H A Dtcg-target-con-set.h21 C_O1_I1(r, r)
22 C_O1_I1(v, r)
23 C_O1_I1(v, v)
24 C_O1_I1(v, vr)
H A Dtcg-target.c.inc3222 return C_O1_I1(r, r);
3324 return C_O1_I1(r, r);
3330 return C_O1_I1(r, r);
3375 return C_O1_I1(v, r);
3377 return C_O1_I1(v, vr);
3387 return C_O1_I1(v, v);
/openbmc/qemu/tcg/riscv/
H A Dtcg-target-con-set.h15 C_O1_I1(r, r)
25 C_O1_I1(v, r)
26 C_O1_I1(v, v)
H A Dtcg-target.c.inc2623 return C_O1_I1(r, r);
2712 return C_O1_I1(r, r);
2724 return C_O1_I1(v, r);
2731 return C_O1_I1(v, v);
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target-con-set.h22 C_O1_I1(r, r)
23 C_O1_I1(w, r)
24 C_O1_I1(w, w)
H A Dtcg-target.c.inc2258 return C_O1_I1(r, r);
2340 return C_O1_I1(w, r);
2380 return C_O1_I1(w, w);
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target-con-set.h15 C_O1_I1(r, r)
H A Dtcg-target.c.inc1558 return C_O1_I1(r, r);
/openbmc/qemu/tcg/tci/
H A Dtcg-target-con-set.h16 C_O1_I1(r, r)
H A Dtcg-target.c.inc72 return C_O1_I1(r, r);
160 return C_O1_I1(r, r);
162 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r);
164 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r);
166 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r);
/openbmc/qemu/tcg/mips/
H A Dtcg-target-con-set.h19 C_O1_I1(r, r)
H A Dtcg-target.c.inc2182 return C_O1_I1(r, r);
2266 return C_O1_I1(r, r);
2268 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r);
2274 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r);
2276 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r);
/openbmc/qemu/tcg/
H A Dtcg.c651 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1), macro
676 #undef C_O1_I1
696 #define C_O1_I1(O1, I1) { .args_ct_str = { #O1, #I1 } }, macro
720 #undef C_O1_I1
740 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1) macro