#
2b2ae0a4 |
| 16-Sep-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128
Use new registers for the output, so that we never overlap the input address, which could happen for user-only. This avoids a "tmp = addr +
tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128
Use new registers for the output, so that we never overlap the input address, which could happen for user-only. This avoids a "tmp = addr + 0" in that case.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-3-richard.henderson@linaro.org>
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#
58f89612 |
| 07-Sep-2023 |
Jiajie Chen <c@jia.je> |
tcg/loongarch64: Implement 128-bit load & store
If LSX is available, use LSX instructions to implement 128-bit load & store when MO_128 is required, otherwise use two 64-bit loads & stores.
Signed-
tcg/loongarch64: Implement 128-bit load & store
If LSX is available, use LSX instructions to implement 128-bit load & store when MO_128 is required, otherwise use two 64-bit loads & stores.
Signed-off-by: Jiajie Chen <c@jia.je> Message-Id: <20230908022302.180442-17-c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
c8b859b4 |
| 07-Sep-2023 |
Jiajie Chen <c@jia.je> |
tcg/loongarch64: Lower bitsel_vec to vbitsel
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-13-c@jia.je> Signe
tcg/loongarch64: Lower bitsel_vec to vbitsel
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-13-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
24c42fde |
| 07-Sep-2023 |
Jiajie Chen <c@jia.je> |
tcg/loongarch64: Lower vector bitwise operations
Lower the following ops:
- and_vec - andc_vec - or_vec - orc_vec - xor_vec - nor_vec - not_vec
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: R
tcg/loongarch64: Lower vector bitwise operations
Lower the following ops:
- and_vec - andc_vec - or_vec - orc_vec - xor_vec - nor_vec - not_vec
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-7-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
e9d7c8cf |
| 07-Sep-2023 |
Jiajie Chen <c@jia.je> |
tcg/loongarch64: Lower add/sub_vec to vadd/vsub
Lower the following ops:
- add_vec - sub_vec
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Mes
tcg/loongarch64: Lower add/sub_vec to vadd/vsub
Lower the following ops:
- add_vec - sub_vec
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-6-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
d8b6fa59 |
| 07-Sep-2023 |
Jiajie Chen <c@jia.je> |
tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-5-c@jia.je> Si
tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-5-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
16288ded |
| 07-Sep-2023 |
Jiajie Chen <c@jia.je> |
tcg/loongarch64: Lower basic tcg vec ops to LSX
LSX support on host cpu is detected via hwcap.
Lower the following ops to LSX:
- dup_vec - dupi_vec - dupm_vec - ld_vec - st_vec
Signed-off-by: Jia
tcg/loongarch64: Lower basic tcg vec ops to LSX
LSX support on host cpu is detected via hwcap.
Lower the following ops to LSX:
- dup_vec - dupi_vec - dupm_vec - ld_vec - st_vec
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-3-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v8.0.0 |
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#
e3205306 |
| 03-Apr-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/loongarch64: Simplify constraints on qemu_ld/st
The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments
tcg/loongarch64: Simplify constraints on qemu_ld/st
The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.2.0 |
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#
7bc76a4c |
| 29-Nov-2022 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/loongarch64: Implement movcond
Reviewed-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
0e95be93 |
| 29-Nov-2022 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/loongarch64: Introduce tcg_out_addi
Adjust the constraints to allow any int32_t for immediate addition. Split immediate adds into addu16i + addi, which covers quite a lot of the immediate space
tcg/loongarch64: Introduce tcg_out_addi
Adjust the constraints to allow any int32_t for immediate addition. Split immediate adds into addu16i + addi, which covers quite a lot of the immediate space. For the hole in the middle, load the constant into TMP0 instead.
Reviewed-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.0.0 |
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#
d3a1727c |
| 20-Dec-2021 |
WANG Xuerui <git@xen0n.name> |
tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <
tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-24-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
251ebcd8 |
| 20-Dec-2021 |
WANG Xuerui <git@xen0n.name> |
tcg/loongarch64: Implement simple load/store ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@
tcg/loongarch64: Implement simple load/store ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-23-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
9ee775cf |
| 20-Dec-2021 |
WANG Xuerui <git@xen0n.name> |
tcg/loongarch64: Implement setcond ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-21-git@xen0n.name>
tcg/loongarch64: Implement setcond ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-21-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
94505c02 |
| 20-Dec-2021 |
WANG Xuerui <git@xen0n.name> |
tcg/loongarch64: Implement br/brcond ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.or
tcg/loongarch64: Implement br/brcond ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-20-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
ff13c196 |
| 20-Dec-2021 |
WANG Xuerui <git@xen0n.name> |
tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathi
tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-19-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
39f54ce5 |
| 20-Dec-2021 |
WANG Xuerui <git@xen0n.name> |
tcg/loongarch64: Implement add/sub ops
The neg_i{32,64} ops is fully expressible with sub, so omitted for simplicity.
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <ric
tcg/loongarch64: Implement add/sub ops
The neg_i{32,64} ops is fully expressible with sub, so omitted for simplicity.
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-18-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
a164010b |
| 20-Dec-2021 |
WANG Xuerui <git@xen0n.name> |
tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4
tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-17-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
fde69301 |
| 20-Dec-2021 |
WANG Xuerui <git@xen0n.name> |
tcg/loongarch64: Implement clz/ctz ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-16-git@xen0n.name>
tcg/loongarch64: Implement clz/ctz ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211221054105.178795-16-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
7257809f |
| 20-Dec-2021 |
WANG Xuerui <git@xen0n.name> |
tcg/loongarch64: Implement deposit/extract ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@am
tcg/loongarch64: Implement deposit/extract ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-14-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
97b2fafb |
| 20-Dec-2021 |
WANG Xuerui <git@xen0n.name> |
tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Dau
tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-13-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
6be08fcf |
| 20-Dec-2021 |
WANG Xuerui <git@xen0n.name> |
tcg/loongarch64: Implement sign-/zero-extension ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4b
tcg/loongarch64: Implement sign-/zero-extension ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-12-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
e3b15766 |
| 20-Dec-2021 |
WANG Xuerui <git@xen0n.name> |
tcg/loongarch64: Implement goto_ptr
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Me
tcg/loongarch64: Implement goto_ptr
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-11-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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