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Searched refs:CS5BBCR (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7710.h29 #define CS5BBCR 0xA4FD0018 macro
H A Dcpu_sh7723.h40 #define CS5BBCR 0xFEC10018 macro
H A Dcpu_sh7724.h41 #define CS5BBCR 0xFEC10018 macro
H A Dcpu_sh7720.h66 #define CS5BBCR (BSC_BASE + 0x18) macro
H A Dcpu_sh7722.h130 #define CS5BBCR 0xFEC10018 macro
/openbmc/u-boot/board/mpr2/
H A Dmpr2.c38 __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
/openbmc/linux/arch/sh/include/mach-common/mach/
H A Dmagicpanelr2.h37 #define CS5BBCR 0xA4FD0018UL macro
/openbmc/u-boot/board/renesas/ap325rxa/
H A Dlowlevel_init.S142 CS5BBCR_A: .long CS5BBCR
/openbmc/u-boot/board/ms7722se/
H A Dlowlevel_init.S184 CS5BBCR_A: .long CS5BBCR ! USB controller
/openbmc/u-boot/board/renesas/MigoR/
H A Dlowlevel_init.S152 CS5BBCR_A: .long CS5BBCR
/openbmc/linux/arch/sh/boards/
H A Dboard-magicpanelr2.c85 __raw_writel(0x00000200, CS5BBCR); in setup_chip_select()