| /openbmc/qemu/target/arm/tcg/ |
| H A D | m_helper.c | 229 qemu_log_mask(CPU_LOG_INT, in v7m_stack_write()
234 qemu_log_mask(CPU_LOG_INT, in v7m_stack_write()
245 qemu_log_mask(CPU_LOG_INT, in v7m_stack_write()
249 qemu_log_mask(CPU_LOG_INT, in v7m_stack_write()
263 qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.LSPERR\n"); in v7m_stack_write()
266 qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.STKERR\n"); in v7m_stack_write()
317 qemu_log_mask(CPU_LOG_INT, in v7m_stack_read()
324 qemu_log_mask(CPU_LOG_INT, in v7m_stack_read()
337 qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n"); in v7m_stack_read()
671 qemu_log_mask(CPU_LOG_INT, in arm_v7m_load_vector()
[all...] |
| /openbmc/qemu/target/microblaze/ |
| H A D | helper.c | 45 qemu_log_mask(CPU_LOG_INT, in mb_unaligned_access_internal()
175 qemu_log_mask(CPU_LOG_INT, in mb_cpu_do_interrupt()
194 qemu_log_mask(CPU_LOG_INT, in mb_cpu_do_interrupt()
224 qemu_log_mask(CPU_LOG_INT, in mb_cpu_do_interrupt()
238 qemu_log_mask(CPU_LOG_INT, in mb_cpu_do_interrupt()
270 qemu_log_mask(CPU_LOG_INT, in mb_cpu_do_interrupt()
273 qemu_log_mask(CPU_LOG_INT, in mb_cpu_get_phys_page_attrs_debug()
277 qemu_log_mask(CPU_LOG_INT, in mb_cpu_get_phys_page_attrs_debug()
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| H A D | op_helper.c | 386 qemu_log_mask(CPU_LOG_INT, "Stack protector violation at " in helper_stackprot()
438 qemu_log_mask(CPU_LOG_INT, "Transaction failed: addr 0x%" PRIx64 in mb_transaction_failed_internal()
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| /openbmc/qemu/target/rx/ |
| H A D | helper.c | 68 qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n"); in rx_cpu_do_interrupt()
79 qemu_log_mask(CPU_LOG_INT, "interrupt 0x%02x raised\n", env->ack_irq); in rx_cpu_do_interrupt()
121 qemu_log_mask(CPU_LOG_INT, "exception 0x%02x [%s] raised\n", in rx_cpu_exec_interrupt()
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| /openbmc/qemu/target/loongarch/tcg/ |
| H A D | op_helper.c | 116 qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA " TARGET_FMT_lx "\n", in helper_ertn()
123 qemu_log_mask(CPU_LOG_INT, "%s: ERA " TARGET_FMT_lx "\n", in helper_ertn()
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| /openbmc/qemu/target/xtensa/ |
| H A D | exc_helper.c | 213 qemu_log_mask(CPU_LOG_INT, in xtensa_cpu_do_interrupt()
238 qemu_log_mask(CPU_LOG_INT, "%s(%d) " in xtensa_cpu_do_interrupt()
251 qemu_log_mask(CPU_LOG_INT, in xtensa_cpu_do_interrupt()
|
| /openbmc/qemu/hw/xtensa/ |
| H A D | mx_pic.c | 137 qemu_log_mask(CPU_LOG_INT, "%s: CPU %d, irq: %08x, changed_irq: %08x\n", in xtensa_mx_pic_update_cpu()
257 qemu_log_mask(CPU_LOG_INT, in xtensa_mx_pic_ext_reg_write()
305 qemu_log_mask(CPU_LOG_INT, in xtensa_mx_pic_set_irq()
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| H A D | pic_cpu.c | 51 qemu_log_mask(CPU_LOG_INT, in check_interrupts()
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| /openbmc/qemu/hw/intc/ |
| H A D | loongson_liointc.c | 150 qemu_log_mask(CPU_LOG_INT, "%s: size=%d, addr=%"HWADDR_PRIx", val=%x\n", in liointc_read()
162 qemu_log_mask(CPU_LOG_INT, "%s: size=%d, addr=%"HWADDR_PRIx", val=%x\n", in liointc_write()
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| H A D | ppc-uic.c | 47 # define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
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| /openbmc/qemu/include/qemu/ |
| H A D | log.h | 21 #define CPU_LOG_INT (1u << 4) macro
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| /openbmc/qemu/target/i386/tcg/system/ |
| H A D | seg_helper.c | 207 qemu_log_mask(CPU_LOG_INT, in x86_cpu_exec_interrupt()
215 qemu_log_mask(CPU_LOG_INT, in x86_cpu_exec_interrupt()
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| H A D | smm_helper.c | 43 qemu_log_mask(CPU_LOG_INT, "SMM: enter\n"); in do_smm_enter()
44 log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); in do_smm_enter()
317 qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n"); in helper_rsm()
318 log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); in helper_rsm()
|
| /openbmc/qemu/target/openrisc/ |
| H A D | interrupt.c | 87 qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n", in openrisc_cpu_do_interrupt()
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| /openbmc/qemu/target/mips/tcg/ |
| H A D | exception.c | 144 qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", in do_raise_exception_err()
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| /openbmc/qemu/target/hppa/ |
| H A D | sys_helper.c | 97 if (qemu_loglevel_mask(CPU_LOG_INT)) { in HELPER()
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| H A D | int_helper.c | 232 if (qemu_loglevel_mask(CPU_LOG_INT)) { in hppa_cpu_do_interrupt()
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| /openbmc/qemu/target/i386/tcg/ |
| H A D | excp_helper.c | 53 qemu_log_mask(CPU_LOG_INT, "check_exception old: 0x%x new 0x%x\n", in check_exception()
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| /openbmc/qemu/target/sparc/ |
| H A D | int32_helper.c | 108 if (qemu_loglevel_mask(CPU_LOG_INT)) { in sparc_cpu_do_interrupt()
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| H A D | int64_helper.c | 142 if (qemu_loglevel_mask(CPU_LOG_INT)) { in sparc_cpu_do_interrupt()
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| /openbmc/qemu/target/s390x/tcg/ |
| H A D | excp_helper.c | 46 qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n", in tcg_s390_program_interrupt()
262 qemu_log_mask(CPU_LOG_INT, in do_program_interrupt()
508 qemu_log_mask(CPU_LOG_INT, "%s: %d at psw=%" PRIx64 ":%" PRIx64 "\n", in s390_cpu_do_interrupt()
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| H A D | misc_helper.c | 611 qemu_log_mask(CPU_LOG_INT, "PER interrupt after 0x%" PRIx64 "\n", in per_raise_exception_log()
660 qemu_log_mask(CPU_LOG_INT, "PER interrupt before 0x%" PRIx64 "\n", in HELPER()
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| /openbmc/qemu/target/loongarch/ |
| H A D | cpu.c | |
| /openbmc/qemu/target/m68k/ |
| H A D | op_helper.c | 230 if (qemu_loglevel_mask(CPU_LOG_INT)) { in cf_interrupt_all()
313 if (qemu_loglevel_mask(CPU_LOG_INT)) { in m68k_interrupt_all()
395 if (qemu_loglevel_mask(CPU_LOG_INT)) { in m68k_interrupt_all()
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| /openbmc/qemu/util/ |
| H A D | log.c | 491 { CPU_LOG_INT, "int",
|