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Searched refs:CPG_PLL3CR (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/clk/renesas/
H A Dclk-sh73a0.c32 #define CPG_PLL3CR 0xdc macro
105 enable_reg += CPG_PLL3CR; in sh73a0_cpg_register_clock()
/openbmc/u-boot/board/renesas/blanche/
H A Dblanche.c33 #define CPG_PLL3CR 0xE61500DC macro
52 writel(0x4F000000, CPG_PLL3CR); in blanche_init_sys()