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Searched refs:CPG_PLL1CR (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/clk/renesas/
H A Dclk-sh73a0.c30 #define CPG_PLL1CR 0x28 macro
99 enable_reg += CPG_PLL1CR; in sh73a0_cpg_register_clock()
H A Dclk-r8a73a4.c28 #define CPG_PLL1CR 0x28 macro
102 u32 value = readl(base + CPG_PLL1CR); in r8a73a4_cpg_register_clock()
/openbmc/u-boot/board/renesas/blanche/
H A Dblanche.c32 #define CPG_PLL1CR 0xE6150028 macro
51 writel(0x4D000000, CPG_PLL1CR); in blanche_init_sys()