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Searched refs:CP0_MVPControl (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/mips/tcg/system/
H A Dcp0_helper.c232 return env->mvp->CP0_MVPControl; in helper_mfc0_mvpcontrol()
524 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { in helper_mtc0_mvpcontrol()
527 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); in helper_mtc0_mvpcontrol()
531 env->mvp->CP0_MVPControl = newval; in helper_mtc0_mvpcontrol()
622 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) in helper_mtc0_vpeconf1()
695 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { in helper_mtc0_tcbind()
709 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { in helper_mttc0_tcbind()
1563 target_ulong prev = env->mvp->CP0_MVPControl; in helper_dvpe()
1570 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); in helper_dvpe()
1581 target_ulong prev = env->mvp->CP0_MVPControl; in helper_evpe()
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/openbmc/qemu/target/mips/
H A Dinternal.h252 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { in mips_vpe_active()
H A Dcpu.h105 int32_t CP0_MVPControl; member
/openbmc/qemu/target/mips/system/
H A Dmachine.c127 VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),