Searched refs:CP0_Config4 (Results 1 – 5 of 5) sorted by relevance
383 .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),408 .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),441 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |485 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |526 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |757 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |798 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |910 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |1006 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
39 int32_t CP0_Config4; member
912 int32_t CP0_Config4; member
1072 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) { in helper_mtc0_entryhi()1260 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) | in helper_mtc0_config4()1269 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; in helper_mtc0_config5()
304 VMSTATE_INT32(env.CP0_Config4, MIPSCPU),