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Searched refs:CP0_Config1 (Results 1 – 13 of 13) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc62 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
84 .CP0_Config1 = MIPS_CONFIG1 |
104 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
124 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
144 .CP0_Config1 = MIPS_CONFIG1 |
165 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
186 .CP0_Config1 = MIPS_CONFIG1 |
207 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
229 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
251 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
[all …]
H A Dgdbstub.c33 if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) { in mips_cpu_gdb_read_register()
89 if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) { in mips_cpu_gdb_write_register()
H A Dcpu.c107 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); in mips_cpu_dump_state()
205 env->CP0_Config1 = env->cpu_model->CP0_Config1; in mips_cpu_reset_hold()
269 if (env->CP0_Config1 & (1 << CP0C1_FP)) { in mips_cpu_reset_hold()
277 if ((env->CP0_Config1 & (1 << CP0C1_FP)) && in mips_cpu_reset_hold()
H A Dkvm.c71 if (kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { in kvm_arch_init_vcpu()
102 if (!kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { in kvm_mips_reset_vcpu()
104 env->CP0_Config1 &= ~(1 << CP0C1_FP); in kvm_mips_reset_vcpu()
595 if (env->CP0_Config1 & (1 << CP0C1_FP)) { in kvm_mips_put_fpu_registers()
674 if (env->CP0_Config1 & (1 << CP0C1_FP)) { in kvm_mips_get_fpu_registers()
876 &env->CP0_Config1, in kvm_mips_put_cp0_registers()
1093 err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG1, &env->CP0_Config1); in kvm_mips_get_cp0_registers()
H A Dinternal.h36 int32_t CP0_Config1; member
H A Dcpu.h857 int32_t CP0_Config1; member
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.h26 int32_t CP0_Config1; member
H A Dtranslate.c1716 !(ctx->CP0_Config1 & (1 << CP0C1_DL)) && in check_nms_dl_il_sl_tl_l2c()
1717 !(ctx->CP0_Config1 & (1 << CP0C1_IL)) && in check_nms_dl_il_sl_tl_l2c()
2298 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { in gen_cop1_ldst()
5540 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1)); in gen_mfc0()
5602 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mfc0()
5620 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mfc0()
6336 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mtc0()
6354 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mtc0()
7016 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1)); in gen_dmfc0()
7078 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmfc0()
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H A Dmicromips_translate.c.inc1867 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
2493 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
H A Dnanomips_translate.c.inc2676 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
2714 if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) {
/openbmc/qemu/target/mips/sysemu/
H A Dmachine.c301 VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
/openbmc/qemu/target/mips/tcg/sysemu/
H A Dcp0_helper.c1054 if ((env->CP0_Config1 & (1 << CP0C1_PC)) && in helper_mtc0_hwrena()
1238 case 1: return other->CP0_Config1; in helper_mftc0_configx()
H A Dtlb_helper.c458 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); in r4k_mmu_init()