Searched refs:CONFIG_SYS_DDR_TIMING_4 (Results 1 – 18 of 18) sorted by relevance
| /openbmc/u-boot/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 66 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 macro
101 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
133 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
165 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
197 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
229 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
261 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
293 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
325 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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| /openbmc/u-boot/include/configs/ |
| H A D | BSC9132QDS.h | 170 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 macro
176 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 macro
182 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 macro
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| H A D | BSC9131RDB.h | 98 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 macro
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| H A D | p1_twr.h | 97 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
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| H A D | MPC8569MDS.h | 102 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
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| H A D | UCP1020.h | 169 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
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| H A D | P1022DS.h | 162 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
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| H A D | P1010RDB.h | 239 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 macro
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| H A D | p1_p2_rdb_pc.h | 304 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
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| /openbmc/u-boot/board/freescale/bsc9132qds/ |
| H A D | ddr.c | 35 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
62 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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| /openbmc/u-boot/board/freescale/p1010rdb/ |
| H A D | ddr.c | 38 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
65 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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| /openbmc/u-boot/board/freescale/p1_twr/ |
| H A D | ddr.c | 44 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, in fixed_sdram()
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| /openbmc/u-boot/board/freescale/bsc9131rdb/ |
| H A D | spl_minimal.c | 45 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); in sdram_init()
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| H A D | ddr.c | 36 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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| /openbmc/u-boot/board/Arcturus/ucp1020/ |
| H A D | ddr.c | 104 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, in fixed_sdram()
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| /openbmc/u-boot/board/freescale/p1_p2_rdb_pc/ |
| H A D | ddr.c | 236 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, in fixed_sdram()
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| /openbmc/u-boot/board/freescale/mpc8569mds/ |
| H A D | mpc8569mds.c | 251 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); in fixed_sdram()
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| /openbmc/u-boot/scripts/ |
| H A D | config_whitelist.txt | 2415 CONFIG_SYS_DDR_TIMING_4
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