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Searched refs:CONFIG_SYS_DDR_TIMING_1_800 (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c38 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744 macro
89 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
121 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A Dspl_minimal.c33 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init()
H A Dddr.c24 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
/openbmc/u-boot/board/freescale/bsc9132qds/
H A Dspl_minimal.c30 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init()
H A Dddr.c23 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
/openbmc/u-boot/include/configs/
H A DBSC9131RDB.h103 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 macro
H A DBSC9132QDS.h145 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 macro
H A DP1010RDB.h244 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 macro
/openbmc/u-boot/board/freescale/p1010rdb/
H A Dddr.c26 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
/openbmc/u-boot/scripts/
H A Dconfig_whitelist.txt2399 CONFIG_SYS_DDR_TIMING_1_800