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Searched refs:CONFIG_SYS_DDR_CONTROL_2 (Results 1 – 15 of 15) sorted by relevance

/openbmc/u-boot/include/configs/
H A DBSC9132QDS.h169 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 macro
175 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 macro
181 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 macro
H A DBSC9131RDB.h97 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 macro
H A Dp1_twr.h96 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 macro
H A DUCP1020.h168 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 macro
H A DP1022DS.h161 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 macro
H A DP1010RDB.h238 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 macro
H A Dp1_p2_rdb_pc.h303 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 macro
/openbmc/u-boot/board/freescale/bsc9132qds/
H A Dddr.c26 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
53 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
/openbmc/u-boot/board/freescale/p1010rdb/
H A Dddr.c29 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
56 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
/openbmc/u-boot/board/freescale/p1_twr/
H A Dddr.c35 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, in fixed_sdram()
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A Dspl_minimal.c36 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); in sdram_init()
H A Dddr.c27 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
/openbmc/u-boot/board/Arcturus/ucp1020/
H A Dddr.c95 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, in fixed_sdram()
/openbmc/u-boot/board/freescale/p1_p2_rdb_pc/
H A Dddr.c227 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, in fixed_sdram()
/openbmc/u-boot/scripts/
H A Dconfig_whitelist.txt2322 CONFIG_SYS_DDR_CONTROL_2