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Searched refs:CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (Results 1 – 13 of 13) sorted by relevance

/openbmc/u-boot/board/terasic/de0-nano-soc/qts/
H A Dpll_config.h52 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 macro
/openbmc/u-boot/board/terasic/sockit/qts/
H A Dpll_config.h52 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 macro
/openbmc/u-boot/board/ebv/socrates/qts/
H A Dpll_config.h52 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 macro
/openbmc/u-boot/board/is1/qts/
H A Dpll_config.h52 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 macro
/openbmc/u-boot/board/devboards/dbm-soc1/qts/
H A Dpll_config.h52 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 macro
/openbmc/u-boot/board/sr1500/qts/
H A Dpll_config.h52 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 macro
/openbmc/u-boot/board/altera/arria5-socdk/qts/
H A Dpll_config.h52 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 macro
/openbmc/u-boot/board/terasic/de10-nano/qts/
H A Dpll_config.h52 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 macro
/openbmc/u-boot/board/altera/cyclone5-socdk/qts/
H A Dpll_config.h52 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 macro
/openbmc/u-boot/board/terasic/de1-soc/qts/
H A Dpll_config.h52 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 macro
/openbmc/u-boot/board/samtec/vining_fpga/qts/
H A Dpll_config.h52 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 macro
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dwrap_pll_config.c108 (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
/openbmc/u-boot/scripts/
H A Dconfig_whitelist.txt815 CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT