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Searched refs:CMCOR_0 (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7269.h24 #define CMCOR_0 0xFFFEC006 macro
H A Dcpu_sh7203.h31 #define CMCOR_0 0xFFFEC006 macro
H A Dcpu_sh7264.h31 #define CMCOR_0 0xFFFEC006 macro
/openbmc/u-boot/arch/sh/lib/
H A Dtime_sh2.c40 writew(CMT_TIMER_RESET, CMCOR_0); in timer_init()