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Searched refs:CLR (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/Documentation/admin-guide/
H A Dmono.rst5 (in the form of .exe files) without the need to use the mono CLR
11 1) You MUST FIRST install the Mono CLR support, either by downloading
21 Once the Mono CLR support has been installed, just check that
50 # Register support for .NET CLR binaries
53 # the Mono CLR runtime (usually /usr/local/bin/mono
55 echo ':CLR:M::MZ::/usr/bin/mono:' > /proc/sys/fs/binfmt_misc/register
/openbmc/linux/drivers/clk/imx/
H A Dclk-pfd.c33 #define CLR 0x8 macro
40 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); in clk_pfd_enable()
100 writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR); in clk_pfd_set_rate()
/openbmc/linux/drivers/clk/mxs/
H A Dclk-pll.c47 writel_relaxed(1 << pll->power, pll->base + CLR); in clk_pll_unprepare()
54 writel_relaxed(1 << 31, pll->base + CLR); in clk_pll_enable()
H A Dclk-imx23.c52 writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR); in clk_misc_init()
63 writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR); in clk_misc_init()
69 writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR); in clk_misc_init()
H A Dclk-imx28.c73 writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR); in mxs_saif_clkmux_select()
90 writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR); in clk_misc_init()
110 writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR); in clk_misc_init()
H A Dclk.h15 #define CLR 0x8 macro
H A Dclk-ref.c35 writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR); in clk_ref_enable()
/openbmc/linux/arch/arm/boot/compressed/
H A Dhead-sharpsl.S132 orr r3, r3, #0x0a @ SET CLR + FLWP
136 bic r3, r3, #2 @ CLR CLE
141 bic r3, r3, #4 @ CLR ALE
/openbmc/linux/drivers/pwm/
H A Dpwm-mxs.c18 #define CLR 0x8 macro
69 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR); in mxs_pwm_apply()
/openbmc/linux/arch/arm/mach-rpc/
H A Dirq.c14 #define CLR 0x04 macro
132 writeb(mask, base + CLR); in iomd_irq_mask_ack()
/openbmc/linux/drivers/pinctrl/freescale/
H A Dpinctrl-mxs.h13 #define CLR 0x8 macro
H A Dpinctrl-mxs.c296 writel(1 << shift, reg + CLR); in mxs_pinconf_group_set()
307 writel(1 << shift, reg + CLR); in mxs_pinconf_group_set()
/openbmc/linux/drivers/gpu/drm/imx/dcss/
H A Ddcss-dev.h16 #define CLR 0x08 macro
22 #define dcss_clr(v, c) writel((v), (c) + CLR)
/openbmc/linux/arch/arm64/net/
H A Dbpf_jit.h134 #define A64_STCLR(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, CLR)
144 #define A64_LDCLRAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, CLR)
/openbmc/qemu/hw/timer/
H A Dsse-timer.c66 FIELD(CNTP_AIVAL_CTL, CLR, 1, 1)
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v3.yaml133 only the {SET,CLR}SPI registers to be used if isolation is required,
/openbmc/linux/drivers/video/fbdev/
H A Dimsttfb.c51 CLR = 6, /* 0x18 */ enumerator
1015 write_reg_le32(par->dc_regs, CLR, bgc); in imsttfb_fillrect()
/openbmc/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc212 C(0x1500, CLR, RR_a, Z, r1, r2, 0, 0, 0, cmpu32)