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Searched refs:CLOCK_CNTL_INDEX (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/drivers/video/
H A Dati_radeon_fb.h250 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); in __INPLL()
261 OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); in __OUTPLL()
H A Dati_radeon_fb.c220 OUTREGP(CLOCK_CNTL_INDEX, in radeon_write_pll_regs()
240 OUTREGP(CLOCK_CNTL_INDEX, in radeon_write_pll_regs()
/openbmc/linux/drivers/video/fbdev/aty/
H A Dradeon_accel.c201 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); in radeonfb_engine_reset()
254 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); in radeonfb_engine_reset()
H A Dradeon_pm.c1483 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_start_mclk_sclk()
1518 OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN); in radeon_pm_start_mclk_sclk()
1639 OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN); in radeon_pm_restore_pixel_pll()
1657 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_restore_pixel_pll()
1684 OUTREG8(CLOCK_CNTL_INDEX+1, 0); in radeon_pm_restore_pixel_pll()
2277 OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN);
2300 OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN);
2430 OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN);
2454 OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
2459 tmp = INREG(CLOCK_CNTL_INDEX);
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H A Dradeon_base.c304 save = INREG(CLOCK_CNTL_INDEX); in radeon_pll_errata_after_data_slow()
306 OUTREG(CLOCK_CNTL_INDEX, tmp); in radeon_pll_errata_after_data_slow()
308 OUTREG(CLOCK_CNTL_INDEX, save); in radeon_pll_errata_after_data_slow()
329 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); in __INPLL()
338 OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); in __OUTPLL()
643 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3; in radeon_probe_pll_params()
1340 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f; in radeon_save_state()
1368 OUTREGP(CLOCK_CNTL_INDEX, in radeon_write_pll_regs()
1386 OUTREGP(CLOCK_CNTL_INDEX, in radeon_write_pll_regs()
H A Daty128fb.c562 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F); in _aty_ld_pll()
570 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); in _aty_st_pll()
696 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX); in aty128_reset_engine()
708 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); in aty128_reset_engine()
1328 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); in aty128_set_pll()
H A Dradeon_monitor.c664 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3; in radeon_fixup_panel_info()
/openbmc/linux/include/video/
H A Daty128.h13 #define CLOCK_CNTL_INDEX 0x0008 macro
H A Dradeon.h307 #define CLOCK_CNTL_INDEX 0x0008 macro
/openbmc/qemu/hw/display/
H A Dati_regs.h31 #define CLOCK_CNTL_INDEX 0x0008 macro
/openbmc/u-boot/include/
H A Dradeon.h309 #define CLOCK_CNTL_INDEX 0x0008 macro