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Searched refs:CLK_TYPE_DIV6P1 (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/drivers/clk/renesas/
H A Drenesas-cpg-mssr.h58 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */ enumerator
75 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
H A Dclk-rcar-gen2.c129 case CLK_TYPE_DIV6P1: /* DIV6 Clock with 1 parent clock */ in gen2_clk_get_rate()
/openbmc/linux/drivers/clk/renesas/
H A Drenesas-cpg-mssr.h36 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */ enumerator
54 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
H A Drenesas-cpg-mssr.c348 case CLK_TYPE_DIV6P1: in cpg_mssr_register_core_clk()
363 if (core->type == CLK_TYPE_DIV6P1) { in cpg_mssr_register_core_clk()